Patent application number | Description | Published |
20130069501 | COMBINED FRAME FOR AN ELECTROMECHANICAL BOX - A combined frame for an electromechanical box has eight transversal beams, eight major connectors and four longitudinal columns. Each transversal beam has a body, two side covers and two fasteners. The side covers are securely mounted on the body and each has a fastening hole. The fasteners are respectively connected to the fastening holes of the side covers. Each major connector is connected to two adjacent transversal beams and has an internal surface, an external surface, a bottom, a top, an abutting wall, two through holes and a mounting hole. The longitudinal columns are connected to the major connectors between the transversal beams and each longitudinal column has a body, two minor connectors and two fixing elements. The minor connectors are respectively and securely mounted in the body and are respectively connected to the major connectors. | 03-21-2013 |
20130249362 | COMBINED FRAME FOR AN ELECTROMECHANICAL BOX - A combined frame for an electromechanical box has eight transversal beams, eight major connectors and four longitudinal columns. Each transversal beam has a body, two side covers and two fasteners. The side covers are securely mounted on the body and each has a fastening hole. The fasteners are respectively connected to the fastening holes of the side covers. Each major connector is connected to two adjacent transversal beams and has an internal surface, an external surface, a bottom, a top, an abutting wall, two through holes and a mounting hole. The longitudinal columns are connected to the major connectors between the transversal beams and each longitudinal column has a body, two minor connectors and two fixing elements. The minor connectors are respectively and securely mounted in the body and are respectively connected to the major connectors. | 09-26-2013 |
20130249363 | COMBINED FRAME FOR AN ELECTROMECHANICAL BOX - A combined frame for an electromechanical box has eight transversal beams, eight major connectors and four longitudinal columns. Each transversal beam has a body, two side covers and two fasteners. The side covers are securely mounted on the body and each has a fastening hole. The fasteners are respectively connected to the fastening holes of the side covers. Each major connector is connected to two adjacent transversal beams and has an internal surface, an external surface, a bottom, a top, an abutting wall, two through holes and a mounting hole. The longitudinal columns are connected to the major connectors between the transversal beams and each longitudinal column has a body, two minor connectors and two fixing elements. The minor connectors are respectively and securely mounted in the body and are respectively connected to the major connectors. | 09-26-2013 |
Patent application number | Description | Published |
20120173922 | APPARATUS AND METHOD FOR HANDLING FAILED PROCESSOR OF MULTIPROCESSOR INFORMATION HANDLING SYSTEM - An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor. | 07-05-2012 |
20120278653 | HANDLING A FAILED PROCESSOR OF MULTIPROCESSOR INFORMATION HANDLING SYSTEM - A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor. | 11-01-2012 |
20140223032 | MEMORY MODULE STATUS INDICATION - Embodiments of the inventive subject matter include receiving, from an interface module, status data for a memory module, wherein the memory module includes a plurality of status indicators. Embodiments further include determining, based on the status data, a set of the plurality of status indicators to illuminate. Embodiments further includes generating, in accordance with said determining the set of the plurality of status indicators based on the status data, a plurality of commands for controlling illumination of the set of the plurality of status indicators. Embodiments further include transmitting the plurality of commands to circuitry of the memory module that controls the plurality of status indicators. | 08-07-2014 |
Patent application number | Description | Published |
20130157389 | Multiple-Patterning Overlay Decoupling Method - A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure | 06-20-2013 |
20130203001 | Multiple-Grid Exposure Method - A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (Δt) such that a sub-pixel shift of the exposed target pattern occurs in the second direction. | 08-08-2013 |
20130232453 | NON-DIRECTIONAL DITHERING METHODS - A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid. | 09-05-2013 |
20130232455 | ERROR DIFFUSION AND GRID SHIFT IN LITHOGRAPHY - The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid. | 09-05-2013 |
20130273474 | Grid Refinement Method - The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S | 10-17-2013 |
20130273475 | Grid Refinement Method - The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n | 10-17-2013 |
20150040079 | Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons. | 02-05-2015 |
20150052489 | LONG-RANGE LITHOGRAPHIC DOSE CORRECTION - A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature. | 02-19-2015 |