Patent application number | Description | Published |
20120167119 | Low-latency communications - A method of handling communications by a computer. A system-call communication routine receives a request of an application to perform a socket-related task on a given socket in a blocking mode. The routine repeatedly performs in alternation polling of one or more input/output (I/O) devices servicing the computer and performing the socket-related task. | 06-28-2012 |
20140089450 | Look-Ahead Handling of Page Faults in I/O Operations - A method for data transfer includes receiving in an input/output (I/O) operation a first segment of data to be written to a specified virtual address in a host memory. Upon receiving the first segment of the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. At least one second page of the host memory is identified, to which a second segment of the data is expected to be written. Responsively to detecting that the first page is swapped out and to identifying the at least one second page, at least the first and second pages are swapped into the host memory. After swapping at least the first and second pages into the host memory, the data are written to the first and second pages. | 03-27-2014 |
20140089451 | Application-assisted handling of page faults in I/O operations - A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page. | 03-27-2014 |
20140089528 | Use of free pages in handling of page faults - A method for data transfer includes receiving in an input/output (I/O) operation data to be written to a specified virtual address in a host memory. Upon receiving the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. Responsively to detecting that the first page is swapped out, the received data are written to a second, free page in the host memory, and the specified virtual address is remapped to the free page. | 03-27-2014 |
20140122828 | Sharing address translation between CPU and peripheral devices - A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory. | 05-01-2014 |
20150029853 | CONGESTION CONTROL ENFORCEMENT IN A VIRTUALIZED ENVIRONMENT - In a data network congestion control in a virtualized environment is enforced in packet flows to and from virtual machines in a host. A hypervisor and network interface hardware in the host are trusted components. Enforcement comprises estimating congestion states in the data network attributable to respective packet flows, recognizing a new packet that belongs to one of the data packet flows, and using one or more of the trusted components and to make a determination based on the congestion states that the new packet belongs to a congestion-producing packet flow. A congestion-control policy is applied by one or more of the trusted components to the new packet responsively to the determination. | 01-29-2015 |
20150212817 | Direct IO access from a CPU's instruction stream - A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs. | 07-30-2015 |
20150222547 | EFFICIENT MANAGEMENT OF NETWORK TRAFFIC IN A MULTI-CPU SERVER - A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network. | 08-06-2015 |
20150269116 | REMOTE TRANSACTIONAL MEMORY - Remote transactions using transactional memory are carried out over a data network between an initiator host and a remote target. The transaction comprises a plurality of input-output (IO) operations between an initiator network interface controller and a target network interface controller. The IO operations are controlled by the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the memory location atomically. | 09-24-2015 |
20150280972 | TRANSPORT-LEVEL BONDING - A network node includes one or more network adapters and a bonding driver. The one or more network adapters are configured to communicate respective data flows over a communication network by applying a transport layer protocol that saves communication state information in a state of a respective network adapter. The bonding driver is configured to exchange traffic including the data flows of an application program that is executed in the network node, to communicate the data flows of the traffic via one or more physical links of the one or more network adapters, and, in response to a physical-transport failure, to switch a given data flow to a different physical link or a different network path, transparently to the application program. | 10-01-2015 |
20160043965 | ACCELERATING AND OFFLOADING LOCK ACCESS OVER A NETWORK - Lock access is managed in a data network having an initiator node and a remote target by issuing a lock command from a first process to the remote target via an initiator network interface controller to establish a lock on a memory location, and prior to receiving a reply to the lock command communicating a data access request to the memory location from the initiator network interface controller. Prior to receiving a reply to the data access request, an unlock command issues from the initiator network interface controller. The target network interface controller determines the lock content, and when permitted by the lock accesses the memory location. After accessing the memory location the target network interface controller executes the unlock command. When the lock prevents data access, the lock operation is retried a configurable number of times until data access is allowed or a threshold is exceeded. | 02-11-2016 |
20160077946 | PAGE RESOLUTION STATUS REPORTING - A method for data transfer includes receiving in a data transfer operation data to be written by a peripheral device to a specified virtual address in a random access memory (RAM) of a host computer. Upon receiving the data, it is detected that a page that contains the specified virtual address is marked as not present in a page table of the host computer. The peripheral device receives a notification that the page is not present and an estimate of a length of time that will be required to make the page available and selects a mode for handling of the data transfer operation depending upon the estimate. | 03-17-2016 |
20160117277 | COLLABORATIVE HARDWARE INTERACTION BY MULTIPLE ENTITIES USING A SHARED QUEUE - A method for interaction by a central processing unit (CPU) and peripheral devices in a computer includes allocating, in a memory, a work queue for controlling a first peripheral device of the computer. The CPU prepares a work request for insertion in the allocated work queue, the work request specifying an operation for execution by the first peripheral device. A second peripheral device of the computer submits an instruction to the first peripheral device to execute the work request that was prepared by the CPU and thereby to perform the operation specified by the work request. | 04-28-2016 |
Patent application number | Description | Published |
20080233616 | Method for Carrying Out the Selective Evolution of Proteins in Vitro - The present invention relates to the production of variants of a protein in an in vitro evolution method, comprising the steps: (A) provision of an in vitro expression system comprising (i) a nucleic acid sequence S which codes for a protein Y which is to be varied, (ii) a target molecule X which is able to bind to the protein Y and/or at least one variant Y′ thereof, (iii) an RNA polymerase (Pol) which is able to transcribe the nucleic acid sequence S, (iv) a reverse transcriptase (RT) which is capable of reverse transcription of transcripts of the nucleic acid sequence S, where either the target molecule X is coupled to Pol and the protein Y is coupled to RT, or the target molecule X is coupled to RT and the protein Y is coupled to Pol, (B)incubation of the in vitro expression system from (A) under conditions which enable transcription, reverse transcription and translation to form variants Y′ of the protein Y and nucleic acid sequences S′ coding therefor, and which favor the formation of variants Y′ with improved binding properties for the target molecule X, (C) isolation and, where appropriate, characterization of those variants Y′ which exhibit improved binding properties for binding to X, and/or isolation of nucleic acid sequence variants S′ coding for Y′. | 09-25-2008 |
20100151517 | METHODS FOR CARRYING OUT THE SELECTIVE EVOLUTION OF PROTEINS IN VIVO - The present invention relates to methods for producing variants of proteins which have improved properties in comparison with the initial protein, the variants being obtained with the aid of an in vivo evolution method. | 06-17-2010 |
20100297642 | METHOD FOR DETERMINING FRAMESHIFT MUTATIONS IN CODING NUCLEIC ACIDS - The present invention relates to a method for identifying frameshift mutations in coding nucleic acid sequences. | 11-25-2010 |
20110119778 | STEGANOGRAPHIC EMBEDDING OF INFORMATION IN CODING GENES - The invention relates to the storage of information in nucleic acid sequences. The invention also relates to nucleic acid sequences containing desired information and to the design, production or use of sequences of this type. | 05-19-2011 |
20140066334 | METHOD FOR THE PRODUCTION OF READING-FRAME-CORRECT FRAGMENT LIBRARIES - The present invention relates to reading-frame-correct fragment libraries, methods for their production, and the use of the fragment libraries for selection of functional polypeptide variants with improved properties. | 03-06-2014 |
20150125949 | STEGANOGRAPHIC EMBEDDING OF INFORMATION IN CODING GENES - The present invention relates to the storage of items of information in nucleic acid sequences. The invention also relates to nucleic acid sequences in which desired items of information are contained, and to the design, production or use of such sequences. | 05-07-2015 |