Patent application number | Description | Published |
20110163373 | Semiconductor device including a voltage controlled termination structure and method for fabricating same - According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device. | 07-07-2011 |
20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 11-24-2011 |
20120211825 | Trench MOSFET and Method for Fabricating Same - According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode. | 08-23-2012 |
20130264636 | Trench FET with Ruggedness Enhancement Regions - According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches. | 10-10-2013 |
20140118032 | Buck Converter Power Package - One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip. | 05-01-2014 |
20140167152 | Reduced Gate Charge Trench Field-Effect Transistor - In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET. | 06-19-2014 |
20140167153 | Trench Fet Having Merged Gate Dielectric - In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode. | 06-19-2014 |
20140374825 | Power Semiconductor Device with Contiguous Gate Trenches and Offset Source Trenches - Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another. | 12-25-2014 |