Patent application number | Description | Published |
20110168784 | Wireless Communication Device for Remote Authenticity Verification of Semiconductor Chips, Multi-Chip Modules and Derivative Products - A wireless tag includes a wireless transceiver, a memory and an antenna all formed on a flexible thin film substrate. The wireless tag is inserted into the packaging material of a microelectronic device to implement tracking and authentication functions. In some embodiments, the wireless communication device stores identity or other identification information for the microelectronic device, and/or the derivative system product incorporating the microelectronic device. The wireless tag may be embedded in the packaging of the microelectronic device. In one embodiment, the wireless tag is embedded in the packaging of a multi-chip package module housing one or more integrated circuits. In this manner, the wireless communication device can be used to track and authenticate the integrated circuits as well as the derivative system products incorporating the integrated circuits. | 07-14-2011 |
20110168785 | System and Method To Embed A Wireless Communication Device Into Semiconductor Packages - A wireless tag includes a wireless transceiver, a memory and an antenna all formed on a flexible thin film substrate. The wireless tag is inserted into the packaging of a microelectronic device to implement tracking and authentication functions. In some embodiments, the wireless communication device stores identity or other identification information for the microelectronic device, and/or the derivative system product incorporating the microelectronic device. In one embodiment, the wireless tag is affixed to a top surface of an integrated circuit chip before encapsulation or lid sealing operation of the packaging process. In this manner, the wireless communication device is embedded in the packaging of the microelectronic device and can be used to track and authenticate the microelectronic device as well as the derivative system products incorporating the microelectronic device. | 07-14-2011 |
20110168786 | System and Method To Embed A Wireless Communication Device Into Semiconductor Packages, including Chip-Scale Packages and 3D Semiconductor Packages - A wireless tag includes a wireless transceiver, a memory and an antenna all formed on a thin film substrate. The wireless tag is inserted into the packaging material of a microelectronic device to implement tracking and authentication functions. In some embodiments, the wireless communication device stores identity or other identification information for the microelectronic device, and/or the derivative system product incorporating the microelectronic device. The wireless tag may be affixed to a package lid of the microelectronic device. The wireless tag may further be affixed to a chip scale package or a three dimensional semiconductor package. In this manner, the wireless communication device can be used to track and authenticate the microelectronic device as well as the derivative system products incorporating the microelectronic device. | 07-14-2011 |
20110169115 | Wireless Communication Device for Remote Authenticity Verification of Semiconductor Chips, Multi-Chip Modules and Derivative Products - A semiconductor package includes a package body with a cavity housing a first integrated circuit die. A wireless tag including a wireless element and an antenna is embedded in the semiconductor package. In one embodiment, the antenna is embedded in the package body of the semiconductor package. In another embodiment, the antenna is formed on or in the first integrated circuit die housed in the semiconductor package. According to another aspect of the present invention, the semiconductor package may be mounted on a printed circuit board and a second antenna is formed on the printed circuit board in electrical connection to the antenna embedded in the semiconductor package. | 07-14-2011 |
20110169641 | System and Method To Embed A Wireless Communication Device Into Semiconductor Packages - A wireless tag includes a wireless transceiver, a memory and an antenna all formed on a thin film substrate. The wireless tag is inserted into the packaging material of a microelectronic device to implement tracking and authentication functions. In some embodiments, the wireless communication device stores identity or other identification information for the microelectronic device, and/or the derivative system product incorporating the microelectronic device. The wireless tag may be embedded in the encapsulation materials of the microelectronic device. The wireless tag may also be embedded in the package filler material of the microelectronic device. In this manner, the wireless communication device can be used to track and authenticate the microelectronic device as well as the derivative system products incorporating the microelectronic device. | 07-14-2011 |
20110186980 | Wireless Element With Antenna Formed On A Thin Film Substrate For Embedding into Semiconductor packages - In one embodiment, a wireless tag includes a wireless transceiver, a memory and an antenna all formed on a thin film substrate where the substrate includes one or more openings formed thereon. The opening in the substrate enables the flow of encapsulation material when the wireless tag is embedded into a semiconductor package. In another embodiment, a wireless tag is attached to the package substrate of a semiconductor package where the thin film substrate of the wireless tag has an opening sufficient to accommodate the integrated circuit die of the semiconductor package. In another embodiment, a wireless tag is formed using a metal film as the antenna and a wireless element attached to the metal film. The wireless tag is attached to the package substrate of a semiconductor package using a non-conductive adhesive. The metal film includes an opening sufficient to accommodate the die of the semiconductor package. | 08-04-2011 |
20110220182 | Solar Panel Tracking and Performance Monitoring Through Wireless Communication - In one embodiment, a wireless device is embedded in a solar panel for providing remote tracking and/or performance monitoring of the solar panel. The wireless device may be a wireless tracking device including a memory for storing the identification or identity information of the solar panel or of the individual solar cells forming the panel. The wireless device may be a wireless tracking and monitoring device to provide both tracking and performance monitoring functions. In another embodiment, the wireless device is affixed to the exposed side of the back sheet of the solar panel but within the junction box interface so that the wireless device is enclosed in the junction box housing. In other embodiments, some of the elements of the wireless device may be embedded in the solar panel while other elements are affixed to the exposed back sheet inside the junction box housing. | 09-15-2011 |
20110233271 | System and Method To Track And Authenticate Semiconductor Chips, Multi-Chip Package Modules, And Their Derivative System Products - A method for providing identity authentication and tracking for a multi-chip package (MCP) module or a designated semiconductor chip formed inside a MCP module where the MCP module is provided with a first communication function includes providing a communication element formed on the MCP base where the communication element includes a memory unit for storing identification information; providing an electrical connection between the communication element and the designated semiconductor chip; accessing by the designated semiconductor chip the information stored in the memory unit of the communication element through the electrical connection; and providing the information stored in the communication element to a system outside of the MCP module through the first communication function where the information is used at least to track or authenticate the MCP module or the designated semiconductor chip of the MCP module. | 09-29-2011 |
20110312286 | Activating Dormant Wireless Circuitry Using Motion or Incident Light - A wireless device includes a controller and a wireless transceiver where the controller is operative to place the wireless transceiver in a low power consumption mode based on predefined energy saving control policy. In one embodiment, the wireless device includes an accelerometer generating an output signal indicative of motion or vibration of the wireless device where the output signal of the accelerometer is applied to cause the wireless transceiver to exit from the low power consumption mode. In another embodiment, the wireless device includes a photovoltaic module generating an output voltage signal indicative of incident light impinging on the photovoltaic module where the output voltage signal of the photovoltaic module is applied to cause the wireless transceiver to exit from the low power consumption mode. | 12-22-2011 |
20120161924 | Automatic Authentication of Electronic Devices - An electronic device with an embedded wireless tag may be authenticated by a linking partner, which may be another electronic device or a data network, before network connection can be established. In some embodiments, the electronic device includes an embedded wireless communicator for communicating with the wireless tag through a wireless link to retrieve identification data for authentication. In other embodiments, the electronic device cooperates with an external wireless communicator to retrieve stored identification data from the embedded wireless tag. In alternate embodiments, an electronic device may authenticate a peripheral device with an embedded wireless tag before connection can be established with the peripheral device. The electronic device may further erase the data stored on the peripheral device when authentication fails. | 06-28-2012 |
20120211058 | Antenna for a Wireless Element Affixed to a Solar Module For Enhancing Communication Range - A solar panel includes a wireless device attached to or embedded in the solar panel where the wireless device includes a wireless transceiver circuit and a memory. In one embodiment, the solar panel includes an antenna formed on the metal frame of the solar panel where the antenna is electrically connected to the wireless device to extend a communication range of the wireless device. In another embodiment, the solar panel includes an antenna formed attached to a junction box of the solar panel. The antenna can be a slot antenna or a patch antenna. | 08-23-2012 |
Patent application number | Description | Published |
20100215139 | COUNTERS AND EXEMPLARY APPLICATIONS - Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C | 08-26-2010 |
20100246305 | REGULATORS REGULATING CHARGE PUMP AND MEMORY CIRCUITS THEREOF - A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage V | 09-30-2010 |
20100253303 | VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO - A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed. | 10-07-2010 |
20100259311 | LEVEL SHIFTERS, INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING THE LEVEL SHIFTERS - A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor. | 10-14-2010 |
20110199063 | INTEGRATED CIRCUITS INCLUDING AN LC TANK CIRCUIT AND OPERATING METHODS THEREOF - An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal. | 08-18-2011 |
20110199152 | INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF - An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node. | 08-18-2011 |
20110267107 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode. | 11-03-2011 |
20110285445 | DRIVE LOOP FOR MEMS OSCILLATOR - Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range. | 11-24-2011 |
20110310690 | VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF - A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator. | 12-22-2011 |
20120013374 | PHASE-LOCK ASSISTANT CIRCUITRY - Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock. | 01-19-2012 |
20120019302 | LOW MINIMUM POWER SUPPLY VOLTAGE LEVEL SHIFTER - A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0. | 01-26-2012 |
20120032731 | CHARGE PUMP DOUBLER - An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor. | 02-09-2012 |
20120044008 | LEVEL SHIFTERS FOR IO INTERFACES - A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device. | 02-23-2012 |
20120161742 | CURRENT GENERATOR AND METHOD OF OPERATING - A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor. | 06-28-2012 |
20120200323 | PHASE-LOCK ASSISTANT CIRCUITRY - A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal. | 08-09-2012 |
20120223752 | PHASE LOCKED LOOP WITH CHARGE PUMP - A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal. | 09-06-2012 |
20120230457 | CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP - A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases. | 09-13-2012 |
20120262212 | MULTIPLE-PHASE CLOCK GENERATOR - A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2 | 10-18-2012 |
20130082754 | PHASE LOCKED LOOP CALIBRATION - An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range. | 04-04-2013 |
20130099767 | DRIVERS HAVING T-COIL STRUCTURES - A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage. | 04-25-2013 |
20130106475 | METHOD OF OPERATING PHASE-LOCK ASSISTANT CIRCUITRY | 05-02-2013 |
20130120884 | INPUT/OUTPUT CIRCUIT WITH INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. | 05-16-2013 |
20130121396 | DECISION FEEDBACK EQUALIZER HAVING PROGRAMMABLE TAPS - A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel. | 05-16-2013 |
20130127433 | METHOD OF OPERATING VOLTAGE REGULATOR - A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating. | 05-23-2013 |
20130141170 | AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING - A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking. | 06-06-2013 |
20130222015 | LEVEL SHIFTERS FOR IO INTERFACES - An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level. | 08-29-2013 |
20130335145 | HIGH-SPEED TRANSIMPEDANCE AMPLIFIER - A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. | 12-19-2013 |
20130342247 | CAPACTIVE LOAD PLL WITH CALIBRATION LOOP - A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage. | 12-26-2013 |
20130346811 | DECISION FEEDBACK EQUALIZER - A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. | 12-26-2013 |
20140002332 | PIXELS FOR DISPLAY | 01-02-2014 |
20140015582 | SLICER AND METHOD OF OPERATING THE SAME - This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal. | 01-16-2014 |
20140015611 | METHOD AND APPARATUS FOR FEEDBACK-BASED RESISTANCE CALIBRATION - A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage. | 01-16-2014 |
20140028350 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode. | 01-30-2014 |
20140028407 | Reconfigurable and Auto-Reconfigurable Resonant Clock - The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance. | 01-30-2014 |
20140037035 | PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS - A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal. | 02-06-2014 |
20140038085 | Automatic Misalignment Balancing Scheme for Multi-Patterning Technology - Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced. | 02-06-2014 |
20140044225 | CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP - A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases. | 02-13-2014 |
20140049243 | CURRENT GENERATOR AND METHOD OF OPERATING - A current generator includes an amplifier having a first terminal configured to receive an input voltage, at least one tunable resistor coupled to a second terminal of the amplifier, a resistor calibration circuit coupled to the at least one tunable resistor, and at least one transistor. A gate of the at least one transistor is coupled to an output of the amplifier, and a terminal of the at least one transistor is coupled to the at least one tunable resistor or a load. The resistor calibration circuit is configured to adjust a resistance setting of the at least one tunable resistor to control a current level of the current generator based on a power supply voltage or a current of a reference resistor. | 02-20-2014 |
20140085009 | AMPLIFIER INDUCTOR SHARING FOR INDUCTIVE PEAKING AND METHOD THEREFOR - A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking. | 03-27-2014 |
20140092511 | INPUT/OUTPUT CIRCUIT HAVING AN INDUCTOR - An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage. | 04-03-2014 |
20140103967 | LEVEL SHIFTERS, METHODS FOR MAKING THE LEVEL SHIFTERS AND METHODS OF USING INTEGRATED CIRCUITS - A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal. | 04-17-2014 |
20140119426 | SLICER AND METHOD OF OPERATING THE SAME - A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node. | 05-01-2014 |
20140126656 | CLOCK DATA RECOVERY CIRCUIT WITH HYBRID SECOND ORDER DIGITAL FILTER HAVING DISTINCT PHASE AND FREQUENCY CORRECTION LATENCIES - A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles. | 05-08-2014 |
20140183652 | DUMMY METAL GATE STRUCTURES TO REDUCE DISHING DURING CHEMICAL-MECHANICAL POLISHING - The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect. | 07-03-2014 |
20140184299 | VOLTAGE LEVEL SHIFTER - A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch. | 07-03-2014 |
20140266114 | METHOD OF OPERATING VOLTAGE REGULATOR - A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit. | 09-18-2014 |
20140266118 | VOLTAGE REGULATOR - A voltage regulator includes a driving circuit, a feedback circuit, first and second control circuits and a resistor. The driving circuit is coupled to an input node and an output node and generates an output voltage at the output node from an input voltage at the input node. The feedback circuit is coupled to the output node and generates a feedback voltage based on the output voltage. The first control circuit is coupled to the feedback circuit and the driving circuit to control the output voltage based on the feedback voltage. The resistor has opposite first and second terminals. The first terminal of the resistor is coupled to the output node. The second control circuit is coupled to the second terminal of the output stage resistor and the feedback circuit to control the feedback voltage based on a regulated voltage at the second terminal of the resistor. | 09-18-2014 |
20140270031 | PHASE INTERPOLATOR WITH LINEAR PHASE CHANGE - Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes. | 09-18-2014 |
20140320169 | CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY - A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode. | 10-30-2014 |
20140347110 | CAPACITIVE LOAD PLL WITH CALIBRATION LOOP - A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage. | 11-27-2014 |
20150014518 | HIGH-SPEED TRANSIMPEDANCE AMPLIFIER - A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node. | 01-15-2015 |
20150035566 | DRIVERS HAVING T-COIL STRUCTURES - A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance. | 02-05-2015 |
Patent application number | Description | Published |
20080215534 | COST-BASED SUBQUERY CORRELATION AND DECORRELATION - Techniques are provided that determine that a query includes at least one subquery that may be correlated or decorrelated. An internal representation of the query that represents the subquery in both correlated and decorrelated form is generated, wherein the internal representation includes at least one virtual table. | 09-04-2008 |
20080222176 | STREAMING XPATH ALGORITHM FOR XPATH EXPRESSIONS WITH PREDICATES - A method and system for evaluating a path query are disclosed. The path query corresponds to a query tree including a plurality of query nodes. At least one query node corresponds to at least one predicate and is at a level. The predicate(s) are evaluated for previous query node(s). The method and system include scanning data nodes of a document and determining if the data nodes match the query nodes. The method and system also include placing data related to the data node in match stacks corresponding to matched query nodes. The data for the query node(s) include attribute(s) corresponding to the predicate(s). The method and system further include propagating a matching of the at least one query node backward to a matching of the at least one previous query node. | 09-11-2008 |
20080313234 | EFFICIENT XML SCHEMA VALIDATION OF XML FRAGMENTS USING ANNOTATED AUTOMATON ENCODING - An XML schema is compiled into an annotated automaton encoding, which includes a parsing table for structural information and annotation for type information. The representation is extended to include a mapping from schema types to states in a parsing table. To validate a fragment against a schema type, it is necessary simply to determine the state corresponding to the schema type, and start the validation process from that state. When the process returns to the state, fragment validation has reached successful completion. This approach is more efficient than a general tree representation. Only the data representation of the schema information is handled, making it much easier than manipulating validation parser code generated by a parser generator. In addition, only one representation is needed for schema information for both document and fragment validation. This approach also provides a basis for incremental validation after update. | 12-18-2008 |
20090012945 | SYSTEM FOR EXECUTING A QUERY HAVING MULTIPLE DISTINCT KEY COLUMNS - A system and computer readable medium for executing a query to access data stored in a database, wherein the query includes a plurality of DISTINCT keys, is disclosed. The system and computer readable medium includes a capture module for identifying each of the plurality of DISTINCT keys in the query and a sort module coupled to the capture module for determining if more than one sort is needed to execute the query, performing a first DISTINCT operation on a first DISTINCT key of the plurality of DISTINCT keys, storing data fetched from the first DISTINCT operation in a master workfile only if more than one sort process is needed to execute the query, and utilizing the master workfile to perform subsequent DISTINCT operations on the other of the plurality of DISTINCT keys. | 01-08-2009 |
20090094258 | OFF-LOADING STAR JOIN OPERATIONS TO A STORAGE SERVER - A method, storage server, and computer readable medium for off-loading star-join operations from a host information processing system to a storage server. At least a first and second set of keys from a first and second dimension table, respectively are received from a host system. Each of the first and second set of keys is associated with at least one fact table. A set of locations associated with a set of foreign key indexes are received from the host system. A set of fact table indexes are traversed. At least a first set of Row Identifiers (“RIDs”) associated with the first set of keys and at least a second set of RIDs associated with the second set of keys are identified. An operation is performed on the first and second sets of RIDs to identify an intersecting set of RIDs. The intersecting set of RIDs are then stored. | 04-09-2009 |
20100042631 | METHOD FOR PARTITIONING A QUERY - Techniques for partitioning a query are provided. The techniques include establishing one or more criterion for partitioning a query, wherein the query comprises one or more tables, materializing a first of the one or more tables, partitioning the first of the one or more tables until the one or more criterion have been satisfied, and partitioning and joining a remainder of the one or more tables of the query. | 02-18-2010 |
20120226693 | DYNAMIC SELECTION OF OPTIMAL GROUPING SEQUENCE AT RUNTIME FOR GROUPING SETS, ROLLUP AND CUBE OPERATIONS IN SQL QUERY PROCESSING - A method, apparatus, and article of manufacture for optimizing a query in a computer system. During compilation of the query, a GROUP BY clause with one or more GROUPING SETS, ROLLUP or CUBE operations is maintained in its original form until after query rewrite. The GROUP BY clause with the GROUPING SETS, ROLLUP or CUBE operations is then translated into a plurality of levels having one or more grouping sets. After compilation of the query, a grouping sets sequence is dynamically determined for the GROUP BY clause with the GROUPING SETS, ROLLUP or CUBE operations based on intermediate grouping sets, in order to optimize the grouping sets sequence. The execution of the grouping sets sequence is optimized by selecting a smallest grouping set from a previous one of the levels as an input to a grouping set on a next one of the levels. Finally, a UNION ALL operation is performed on the grouping sets. | 09-06-2012 |
20140067794 | DATABASE GROUPING SET QUERY - Embodiments relate to a method, system, and computer program product for processing database grouping set query. The method includes receiving a grouping set query request; the grouping set query request including a plurality of groups and determining via said grouping set query request a plurality of to be assigned child tasks for parallel processing. Subsequently, one or more of the groups are assigned as child tasks to be parallel processed based on logical relationship among the groups and the number of available parallel child tasks determined and the parallel child tasks are executed to generate grouping set query result. | 03-06-2014 |
Patent application number | Description | Published |
20120072280 | Tracking Conversions - This specification describes technologies relating to content presentation. In general, one aspect of the subject matter described in this specification can be embodied in methods that include the actions of presenting one or more ads to a user; receiving point of sale receipt information from the user, where the receipt image is associated with a redemption of a first ad of the one or more ads presented to the user, the redemption occurring at a physical retail location; processing the receipt information, using one or more processors, to extract text associated with the receipt information; determining that the extracted text associated with the receipt information is associated with the first ad presented to the user; and logging a conversion for the first ad. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. | 03-22-2012 |
20120140914 | RINGBACK ADVERTISING - Methods, systems, and apparatus, including computer program products, in which an indication of a telephone call being placed from a calling number is received, and a determination is made of an audio advertisement to play based on the calling number. The audio advertisement is played based on the determination. | 06-07-2012 |
20120143701 | RE-PUBLISHING CONTENT IN AN ACTIVITY STREAM - Methods, systems, and apparatus, including computer programs encoded on a computer-readable storage medium, for providing a method for re-publishing content that is provided by a content publisher to a user. A method includes providing an advertisement for display to a user in a slot, the advertisement including a first annotation providing information for or about re-publishing the advertisement; receiving a request to re-publish the advertisement to one or more individuals or groups associated with the user in a social context; and providing the advertisement as part of an activity stream for a social application, including presenting the advertisement in the activity stream for the user. | 06-07-2012 |
20130035994 | SYSTEM AND METHOD FOR SHARING CONTENT ON THIRD-PARTY MOBILE APPLICATIONS - Methods and systems are provided for allowing users to recommend advertisements displayed in a third-party application running on a user device while not granting the third-party application privileges to send such recommendations on behalf of the user. A social network application installed on the user device, and separate from the third-party application, acts as a proxy for advertisement recommendation requests (e.g., indications that a user wishes to recommend an advertisement displayed), and a user is required to confirm all such recommendation actions. In this manner, a third-party application (e.g., a “malicious third-party application) cannot send advertisement recommendation requests, and/or requests to undo such recommendations, on its own as if it were the user. | 02-07-2013 |
20130036016 | SYSTEM AND METHOD FOR SHARING CONTENT ON THIRD-PARTY MOBILE APPLICATIONS - Methods and systems are provided for allowing users to recommend advertisements displayed in a third-party application running on a user device while not granting the third-party application privileges to send such recommendations on behalf of the user. A social network application installed on the user device, and separate from the third-party application, acts as a proxy for advertisement recommendation requests (e.g., indications that a user wishes to recommend an advertisement displayed), and a user is required to confirm all such recommendation actions. In this manner, a third-party application (e.g., a “malicious third-party application) cannot send advertisement recommendation requests, and/or requests to undo such recommendations, on its own as if it were the user. | 02-07-2013 |
20130036304 | Share cookie on native platform in mobile device without having to ask for the user's login information - Methods, apparatuses, and computer-readable media for obtaining a limited ID cookie for ad targeting are disclosed. A client requests a limited ID cookie from a cookie making module (CMM), which sends a personal cookie to a verification module for verification. After verification, verification module sends a user ID with user information to CMM. CMM creates the limited ID cookie, and the limited ID cookie is sent to the client. The limited ID cookie is sent to an ads server which utilizes the limited ID cookie to target ads towards the user. | 02-07-2013 |
20130091441 | DETERMINING INTENT OF A RECOMMENDATION ON A MOBILE APPLICATION - Methods and systems are provided for determining the intent of a recommendation made by a user of a mobile application where the application includes a plurality of separable components, any one or more of which the recommendation can apply to. An application in which a user recommendation control is provided for presentation to a user also includes a tag indicating how a recommendation of the application should be interpreted with respect to the components included therein. The tag can be set by the application developer and can be in the form of text (e.g., a keyword or term) or a uniform resource locator (URL). Where a tag references multiple components of an application, a recommending user can be presented with a recommendation intent query. The recommendation intent query allows a user to designate one or more components of the application to which the user's recommendation should be attributed. | 04-11-2013 |
20130254301 | SYNCHRONOUS COMMUNICATION SYSTEM AND METHOD - A method, computer program product, and computing system for providing a plurality of users of a social network with the ability to indicate affinity with an electronic object. An indication is received from a first user of the plurality of users to initiate an object-specific, synchronous communication session concerning the electronic object. Electronic invitations to join the object-specific, synchronous communication session are provided to one or more invited users of the plurality of users of the social network. A request is received, from at least one of the invited users, to join the object-specific, synchronous communication session. The object-specific, synchronous communication session is provided for the first user and the at least one of the invited users. | 09-26-2013 |
20130347078 | Aggregating Online Activities - The disclosure includes a system and method for automatically authorizing data transfer from a third party service to a user device. The system includes a processor and a memory storing instructions that, when executed, cause the system to: receive a request for data from a user of a user device; receive information associated with the user and information associated with the user device; determine whether the user has previously provided authorization for a particular application available on the third party site; determine whether the user has previously provided authorization for the user device; and if the user has previously provided authorization for a particular application available on the third party site or has previously provided authorization for the user device, send data to the user device. | 12-26-2013 |
20140108152 | Managing Social Network Relationships Between A Commercial Entity and One or More Users - Systems and methods for managing relationships between a commercial entity and one or more of a plurality of users is described. One of the methods includes receiving data regarding a first opinion of one of the users. The first opinion is concerned with a first product/service. The user has a user identity (ID), the commercial entity has a commercial entity ID, the first product has a first product ID, and the first service has a first service ID. The method further includes mapping the first opinion data with the user ID and the commercial entity ID and the first product ID or the first service ID. The method includes creating data regarding a first sentiment group within a social network account of the commercial entity based on the mapped first opinion data. The method includes assigning the user ID to the first sentiment group data. | 04-17-2014 |
20140379795 | SMART NOTIFICATIONS IN A SOCIAL NETWORKING SITE - A method and system are disclosed for creating and modifying calendar events in a social networking site environment. On receiving a user request to modify a data entry describing a previously scheduled event or on detecting a change to a data entry describing a previously scheduled event, a synchronous communication session is initiated among the event participants. Subsequent to initiating a synchronous communication session, the data entry describing the previously scheduled event is modified based at least in part on at least one of the user request of the synchronous communication. On receiving a user request to add a new data entry describing a new event, a synchronous communication session is initiated for all event participants. Subsequent to the initiation of the synchronous communication session, the data entry for the new event is added based on at least one of the user request of the synchronous communication. | 12-25-2014 |
20150032820 | USING A DIGITAL IMAGE IN A SOCIAL NETWORKING SYSTEM - Systems and methods for using a digital image in a social networking system may use digital image to identify a physical entity. Information about the identified physical entity may be provided to an electronic display for review by a user. The user may perform a social networking action with the identified physical entity or a website associated with the physical entity. Social networking actions may include rating or commenting about the physical entity or the associated website via a social networking system. Social networking actions may also include sharing information about the physical entity or associated website with another user via the social networking system. | 01-29-2015 |
Patent application number | Description | Published |
20090027525 | Techniques For Reducing Color Artifacts In Digital Images - A technique for reducing artifacts in a digital image, in accordance with one embodiment, includes receiving a stream of raw filter pixel data representing the image. The raw filter pixel data is interpolating to produce red, green-on-red row, green-on-blue row and blue pixel data for each pixel. An artifact in one or more given pixels is reduced as a function of a difference between the green-on-red row and green-on-blue row pixel data of each of the given pixels to generate adjusted interpolated pixel data. | 01-29-2009 |
20090154822 | Image distortion correction - Methods and systems for reducing or eliminating distortion in an image are described. The approach generally involves determining the distortion introduced by a lens, and modifying a captured image to reduce that distortion. In one embodiment, the distortion information associated with a lens is determined. The distortion information is stored. A captured image taken by that lens is processed, with reference to the distortion information. | 06-18-2009 |
20090168887 | One step sub-pixel motion esitmation - A novel Lucas-Kanade sub-pixel motion estimation method is provided. The motion estimation algorithm enables the estimating of a motion vector with reduced computation cost while maintaining high sub-pixel accuracy. The novel algorithm consists of two processing stages. In the first stage, a conventional motion estimation method is applied to obtain the motion vector at integer-pixel level. In the second stage, the Lucas-Kanade algorithm is applied to improve the motion vector to sub-pixel accuracy based on gradient information. Experimental result shows that the proposed method reaches comparable PSNR performance as conventional ⅛-pel algorithm but with significant saving on computation cost. | 07-02-2009 |
20100103310 | FLICKER BAND AUTOMATED DETECTION SYSTEM AND METHOD - A flicker band automated detection system and method are presented. In one embodiment an incidental motion mitigation exposure setting method includes receiving image input information; performing a motion mitigating flicker band automatic detection process; and implementing exposure settings based upon results of the motion mitigating flicker band automatic detection process. The auto flicker band detection process includes performing a motion mitigating process on an illumination intensity indication. Content impacts on an the motion mitigated illumination intensity indication are minimized. The motion mitigated illumination intensity indication is binarized. A correlation of the motion mitigated illumination intensity and a reference illumination intensity frequency is established. | 04-29-2010 |
20100290769 | OPTICAL IMAGE STABILIZATION IN A DIGITAL STILL CAMERA OR HANDSET - An optical image stabilization system for a camera module is disclosed. The stabilization system comprises a voice coil motor (VCM), at least one digital gyroscope for receiving signals from the VCM, and an angular velocity sensor for receiving signals from the digital gyroscope and outputting an angular position error signal. The stabilization system further comprises signal processing logic for receiving the error signal, and comparing the error signal to a reference signal and providing a stabilized image based upon that comparison, wherein the hard-coded logic, digital gyroscope and rate and position sensor resides on the same chip. | 11-18-2010 |
20110178707 | APPARATUS AND METHODOLOGY FOR CALIBRATION OF A GYROSCOPE AND A COMPASS INCLUDED IN A HANDHELD DEVICE - Novel techniques for estimating compass and gyroscope biases for handheld devices are disclosed. The handheld devices can include wireless phones, navigational devices and video gaming systems. The compass bias can be determined by causing a small movement of the handheld device and comparing the data obtained from the compass with the data obtained from the gyroscope. The gyroscope bias can be determined by obtaining a quaternion based angular velocity term of the handheld device when the accelerometer and compass data are reliable, and then comparing the angular velocity term to with the gyro data estimate the gyro bias. When the compass and/or the accelerometer data are unreliable, a previously determined quaternion angular velocity term is used, which was determined when the compass and the accelerometer were providing reliable data. The gyroscope bias can also be determined by measuring gyroscope biases at various temperatures in a non-factory setting, and storing that data in a memory, and using the data to estimate gyro biases when the accelerometer and/or the compass data are unreliable. | 07-21-2011 |
20120007713 | HANDHELD COMPUTER SYSTEMS AND TECHNIQUES FOR CHARACTER AND COMMAND RECOGNITION RELATED TO HUMAN MOVEMENTS - Systems and methods for human hand gesture recognition through a training mode and a recognition mode are disclosed. In the training mode, a user can move a handheld device with a hand gesture intended to represent a command. Sensors within the handheld device can record raw data, which can be processed to obtain a set of values corresponding to a set of discrete features, which is stored in a database and associated with the intended command. The process is repeated for various hand gestures representing different commands. In the recognition mode, the user can move the handheld device with a hand gesture. A computer system can compare a set of values corresponding to a set of discrete features derived from the hand gesture with the sets of values stored in the database, select a command with the closest match and displays and/or executes the command. | 01-12-2012 |
20120072166 | DEDUCED RECKONING NAVIGATION WITHOUT A CONSTRAINT RELATIONSHIP BETWEEN ORIENTATION OF A SENSOR PLATFORM AND A DIRECTION OF TRAVEL OF AN OBJECT - Systems, methods, and apparatus for performing deduced reckoning navigation without a constraint relationship between orientation of a sensor platform and a direction of travel of an object are described herein. A sensor fusion component can be configured to receive data from sensors of a sensor platform coupled to a pedestrian; and generate world coordinate information based on the data. Further, a gait recognition component can be configured to record one or more walking patterns of the pedestrian in a training database; and determine whether the world coordinate information is associated with a walking pattern of the one or more walking patterns. Furthermore, a position estimation component can be configured to estimate a position of the pedestrian based on the world coordinate information if the world coordinate information is associated with the walking pattern, regardless of an orientation of the sensor platform with respect to the position of the pedestrian. | 03-22-2012 |
20120200497 | HIGH FIDELITY REMOTE CONTOLLER DEVICE FOR DIGITAL LIVING ROOM - Described herein is an intelligent remote controlling device. The device can include a six-axis motion sensor to accurately track three dimensional hand motions. For example, the sensors can include a three-axis accelerometer and a three-axis gyroscope. The remote control device can also include a processing unit integrated with the motion sensors in a single module. The processing unit can convert data regarding the hand motion to data regarding a cursor motion for a cursor that will be displayed on a screen of an electronic device. The processing unit can be integrated with the motion sensors in a single module. The processing unit can include at least two modes of functionality corresponding to different types of hand motion: a one to one mode where the cursor directly tracks the hand motion and a non-linear mode that filters data from the motion sensors to eliminate hand jitter. | 08-09-2012 |
20130197845 | N-USE AUTOMATIC CALIBRATION METHODOLOGY FOR SENSORS IN MOBILE DEVICES - A method, system and computer readable medium for calibrating an accelerometer in a portable device is disclosed. The method, system and computer readable medium comprises receiving data from the accelerometer, and providing accelerometer samples from the data based upon one or more selection rules that adaptively selects data that satisfy certain criteria. The method system and computer readable medium also includes fitting the accelerometer samples to a mathematical mode. The method system and computer readable medium further includes providing a bias of the accelerometer based upon a center of the mathematical model. | 08-01-2013 |
20130271372 | HIGH FIDELITY REMOTE CONTOLLER DEVICE FOR DIGITAL LIVING ROOM - Described herein is an intelligent remote controlling device (e.g. a mobile phone). The device can include a six-axis motion sensor to accurately track three dimensional hand motions. For example, the sensors can include a three-axis accelerometer and a three-axis gyroscope. The remote control device can also include a processing unit integrated with the motion sensors in a single module. The processing unit can convert data regarding the hand motion to data regarding a cursor motion for a cursor that will be displayed on a screen of an electronic device. The processing unit can be integrated with the motion sensors in a single module (e.g. an integrated circuit chip (IC)). The processing unit can include at least two modes of functionality corresponding to different types of hand motion: a one to one mode where the cursor directly tracks the hand motion and a non-linear mode that filters data from the motion sensors to eliminate hand jitter. | 10-17-2013 |
20140046586 | DEDUCED RECKONING NAVIGATION WITHOUT A CONSTRAINT RELATIONSHIP BETWEEN ORIENTATION OF A SENSOR PLATFORM AND A DIRECTION OF TRAVEL OF AN OBJECT - Systems, methods, and apparatus for performing deduced reckoning navigation without a constraint relationship between orientation of a sensor platform and a direction of travel of an object are described herein. A sensor fusion component can be configured to receive data from sensors of a sensor platform coupled to a pedestrian; and generate world coordinate information based on the data. Further, a gait recognition component can be configured to record one or more walking patterns of the pedestrian in a training database; and determine whether the world coordinate information is associated with a walking pattern of the one or more walking patterns. Furthermore, a position estimation component can be configured to estimate a position of the pedestrian based on the world coordinate information if the world coordinate information is associated with the walking pattern, regardless of an orientation of the sensor platform with respect to the position of the pedestrian. | 02-13-2014 |
20140278183 | HEADING CONFIDENCE INTERVAL ESTIMATION - An inertial measurement system is disclosed. The inertial measurement system has an accelerometer processing unit that generates a calibrated accelerometer data. The inertial measurement system further includes a magnetometer processing unit generates a calibrated magnetometer data, and a gyroscope processing unit generates a calibrated gyroscope data. Using the calibrated accelerometer data, the calibrated magnetometer data, and the calibrated gyroscope data, the inertial measurement system generates a heading angle error indicative of the accuracy of the heading angle error. | 09-18-2014 |
Patent application number | Description | Published |
20100104221 | METHOD AND SYSTEM FOR FRAME ROTATION WITHIN A JPEG COMPRESSED PIPELINE - A system and methods for rotating and compressing digital image data is presented. The system includes an image sensor that vertically and horizontally flips a digital image, an image processor that converts the image into the YCbCr color space, reorder buffers that divide the YCbCr component data into component blocks and rotate the component blocks, and a JPEG encoder that applies JPEG compression to the rotated component blocks. The JPEG encoder differentially encodes DC coefficients of the component blocks in an order that corresponds to the desired rotated image. An index is created by the JPEG encoder that allows for the reconstruction and storing of the rotated component blocks as a rotated JPEG image. | 04-29-2010 |
20100177203 | APPARATUS AND METHOD FOR LOCAL CONTRAST ENHANCED TONE MAPPING - Methods and systems for enhancing an image. Respective local contrast values are determined for selected pixels of the image by, for each selected pixel, adjusting a respective luminance value of the pixel by an average luminance value of neighboring pixels to obtain the local contrast value. Respective tone-mapped values are determined for further selected pixels in the image based on a global luminance value representing the image. The local contrast values and the tone-mapped values are combined, respectively, for the corresponding pixels in the image to produce the enhanced image. | 07-15-2010 |
20110273546 | SYSTEMS AND METHODS FOR PRESENCE DETECTION - Systems and methods are provided for presence detection using an image system. The image system may be a camera that is integrated into an electronic device. In some embodiments, the image system can accommodate multiple operating modes of the electronic device. For example, when the electronic device is operating in a normal power mode, control circuitry of the image system can detect when a user has left and is no longer using the electronic device. When the electronic device is operating in a power saving mode, the control circuitry can detect user presence (e.g., when a user has come back to the electronic device). In some embodiments, the control circuitry can adjust for both gradual and sudden light changes. | 11-10-2011 |
20120044375 | IMAGING SYSTEMS WITH FIXED OUTPUT SIZES AND FRAME RATES - An imaging system may include an image sensor and an image encoder that encodes images from the image sensor with fixed output sizes and frame rates. The image encoder may encode images from the image sensor into an image format such as a Joint Photographic Experts Group (JPEG) format. The image encoder may insert padding data between image blocks in the encoded data to compensate in real time for variations in the encoded size of an image. The amount of padding data inserted by the encoder may be calculated to ensure the encoded image has a file size close to, but not greater than, the required fixed output size. If needed, the encoder may add additional padding data after the image blocks are encoded in a blanking period before a subsequent image is encoded so that the final size of the encoded image is equal to the required output size. | 02-23-2012 |
20120188386 | SYSTEMS AND METHODS FOR LUMINANCE-BASED SCENE-CHANGE DETECTION FOR CONTINUOUS AUTOFOCUS - Imaging systems with image sensors and image processing circuitry are provided. The image processing circuitry may identify motion and perform autofocus (e.g., continuous autofocus) using images captured by an image sensor. Auto exposure metrics such as average luminance values and autofocus statistics such as sharpness scores may be calculated for each image. The auto exposure metrics may be used to calculate motion scores and identify directional motion between a series of captured images. The motion scores may be used with the sharpness scores to determine when to perform autofocus functions such as when to refocus a lens for a continuous autofocus application. For example, the motion scores may be monitored to identify motion that exceeds a given magnitude and duration. After identification of motion, motion scores and sharpness scores may be used to determine when a given scene has stabilized and when the lens should be refocused. | 07-26-2012 |
20130321676 | Green Non-Uniformity Correction - Systems and methods for correcting green channel non-uniformity (GNU) are provided. In one example, GNU may be corrected using energies between the two green channels (Gb and Gr) during green interpolation processes for red and green pixels. Accordingly, the processes may be efficiently employed through implementation using demosaic logic hardware. In addition, the green values may be corrected based on low-pass-filtered values of the green pixels (Gb and Gr). Additionally, green post-processing may provide some defective pixel correction on interpolated greens by correcting artifacts generated through enhancement algorithms. | 12-05-2013 |
20130321700 | Systems and Methods for Luma Sharpening - Systems, methods, and devices for sharpening image data are provided. One example of an image signal processing system includes a YCC processing pipeline that includes luma sharpening logic. The luma sharpening logic may sharpen the luma component while avoiding sharpening some noise. Specifically, a multi-scale unsharp mask filter may obtain unsharp signals by filtering an input luma component, and sharp component determination logic may determine sharp signals representing differences between the unsharp signals and the luma component. Sharp lookup tables may “core” the sharp signals, which may prevent some noise from being sharpened. Output logic may determine a sharpened output luma signal by combining the sharp signals with, for example, luma component or one of the unsharp signals. | 12-05-2013 |
20130329098 | Systems and Methods for Defective Pixel Correction with Neighboring Pixels - The present disclosure generally relates to systems and methods for image data processing. In certain embodiments, an image processing pipeline may detect and correct a defective pixel of image data acquired using an image sensor. The image processing pipeline may receive an input pixel of the image data acquired using the image sensor. The image processing pipeline may then identify a set of neighboring pixels having the same color component as the input pixel and remove two neighboring pixels from the set of neighboring pixels thereby generating a modified set of neighboring pixels. Here, the two neighboring pixels correspond to a maximum pixel value and a minimum pixel value of the set of neighboring pixels. The image processing pipeline may then determine a gradient for each neighboring pixel in the modified set of neighboring pixels and determine whether the input pixel includes a dynamic defect or a speckle based at least in part on the gradient for each neighboring pixel in the modified set of neighboring pixels. | 12-12-2013 |
20140050360 | SYSTEMS AND METHODS FOR PRESENCE DETECTION - Systems and methods are provided for presence detection using an image system. The image system may be a camera that is integrated into an electronic device. In some embodiments, the image system can accommodate multiple operating modes of the electronic device. For example, when the electronic device is operating in a normal power mode, control circuitry of the image system can detect when a user has left and is no longer using the electronic device. When the electronic device is operating in a power saving mode, the control circuitry can detect user presence (e.g., when a user has come back to the electronic device). In some embodiments, the control circuitry can adjust for both gradual and sudden light changes. | 02-20-2014 |
Patent application number | Description | Published |
20080239955 | ADAPTIVE CROSS-NETWORK MESSAGE BANDWIDTH ALLOCATION BY MESSAGE SERVERS - In one embodiment, a network device is described as including a rate monitor to monitor an actual individual message rate of event messages sent from each one of a plurality of sending devices operatively in communication with the network device, an allocator to allocate an individual message rate limit to each of the plurality of sending devices, and a communication module to communicate a rate limit instruction to at least one of the sending devices, the rate limit instruction to limit the transmission rate of event messages. | 10-02-2008 |
20080301506 | SYSTEM DIAGNOSTICS WITH DYNAMIC CONTEXTUAL INFORMATION OF EVENTS - A network device and a method for monitoring operational messages is described. The method comprises monitoring an occurrence of an operational message of the network device, and storing dynamic context information at the time that the operational message occurred. The stored dynamic context information is then associated with the operational message. The operational message (e.g., a syslog message) may be stored together with the dynamic context information in a metalog memory and may comprise a snapshot of a procedure stack, the procedure stack including information indicative of a sequence of procedure invocations. | 12-04-2008 |
20090003345 | NETWORK DEVICE DYNAMIC HELP - There are provided a method, system, logic and network device to provide additional information and at least one recommended action relating to error information reported by a feature module of the network device. The method comprises generating a request that includes error information reported by a feature module of a network device, the error information including one or more runtime parameters associated with the network device. The method further comprises transmitting the generated request and receiving a response to the request including additional information and the at least one recommended action relating to the error information, the additional information and the at least one recommended action being based at least in part on the one or more runtime parameters. The network device comprises a feature module to report error information including one or more runtime parameters associated with the network device, a help module to generate a request including the error information reported by the feature module and to receive a response to the request, the response including additional information and at least one recommended action relating to the error information, the additional information and the at least one recommended action being based at least in part on the one or more runtime parameters, and a communication module to transmit the generated request and to receive the response to the request. | 01-01-2009 |
20100042820 | SELF-RESTARTING NETWORK DEVICES - A method and apparatus for self-monitoring to identify an occurrence of a threshold and rebooting in response to the occurrence of the threshold is provided. In an embodiment, a data processing apparatus comprises one or more processors; logic coupled to the one or more processors and comprising one or more stored sequences of instructions which, when executed by one or more processors, cause the one or more processors to obtain a threshold associated with the apparatus; self-monitor the apparatus to identify an occurrence of the threshold; and self-reboot the apparatus responsive to the occurrence of the threshold. | 02-18-2010 |
20110055637 | ADAPTIVELY COLLECTING NETWORK EVENT FORENSIC DATA - In an embodiment, a data processing system comprises a repository configured to store a plurality of event message definitions for error messages, syslog messages, or other notification messages that may be emitted by one or more managed network elements; event annotation logic coupled to the data repository and configured to receive and store one or more annotations to each of the event message definitions, wherein each of the annotations specifies event context information to be collected in the managed network elements when an associated event message occurs; event forensics definitions generator logic coupled to the event annotation logic and configured to generate an event forensics definitions file capable of interpretation by one or more managed network elements and comprising event type identifiers and context information identifiers for context information to be collected, and configured to cause distributing the event forensics definitions file to the one or more managed network elements. | 03-03-2011 |
20120008498 | PERFORMING PATH-ORIENTED SYSTEMS MANAGEMENT - A method is disclosed for transmitting system management requests to computer systems along a network path using a network control protocol, such as RSVP. For example, an originating node may send a single system management request along a path to a destination node using a network control protocol. Each computer system along the network path may analyze the network control protocol message to determine whether the message contains a system management request. If a system management request is found in the message, the computer system may perform the system management function identified in the request, and respond to it. | 01-12-2012 |
20120110371 | SELF-RESTARTING NETWORK DEVICES - A method and apparatus for self-monitoring to identify an occurrence of a threshold and rebooting in response to the occurrence of the threshold is provided. In an embodiment, a data processing apparatus comprises one or more processors; logic coupled to the one or more processors and comprising one or more stored sequences of instructions which, when executed by one or more processors, cause the one or more processors to obtain a threshold associated with the apparatus; self-monitor the apparatus to identify an occurrence of the threshold; and self-reboot the apparatus responsive to the occurrence of the threshold. | 05-03-2012 |
20120324106 | ADAPTIVE CROSS-NETWORK MESSAGE BANDWIDTH ALLOCATION BY MESSAGE SERVERS - The network device is described that comprises an allocator to adaptively allocate respective event message rate limits to client network devices that is in communication with an event-based system logging server to send event messages to the logging server for processing. The adaptively allocated event message rate limits are communicated to the client network devices so that limiting of a global rate of event messages received by the logging server comprises limiting the respective rates at which the client network devices can transmit event messages to the logging server. Measurement of respective event message rates comprises a count of event messages actually received by the logging server from the corresponding client device within a defined time window. | 12-20-2012 |
20130067078 | SYSTEM AND METHOD FOR PROVIDING A SCRIPT-BASED COLLECTION FOR DEVICES IN A NETWORK ENVIRONMENT - A method is provided in one example and includes verifying a storage capacity of a network element coupled to an end device over a network connection. The method also includes executing script provided in the network element, which is configured for exchanging packets in a network environment. The script initiates a collection of data being retrieved from the end device. The data can be Fault, Configuration, Accounting, Performance, and Security (FCAPS) data associated with the end device. The data collected from the end device is communicated to a next destination. | 03-14-2013 |
20140173591 | DIFFERENTIATED SERVICE LEVELS IN VIRTUALIZED COMPUTING - In one implementation, a host provides virtualized computing to one or more customer networks. The virtualized computing may include hardware virtualization quantified in the resources of the virtual machines, services virtualization quantified in the quantity or types of services performed on host, or processing virtualization quantified by process occurrences. When the host receives a request for computing virtualization from a user device, the host derives an authentication value and accesses a virtualization service level from a memory. The host is configured to deliver the computing virtualization to the user device according the virtualization service level. | 06-19-2014 |
Patent application number | Description | Published |
20100270897 | INDUSTRIAL COMPUTER CHASSIS STRUCTURE WITH POWER SOURCE DISPOSED CENTRALLY - An industrial computer chassis structure is mainly to partition at least two motherboard sections in the shell of the computer chassis, in each of which a motherboard tray capable of being pulled and drawn is arranged and is provided for placing a motherboard therein. Meanwhile, the two motherboard sections are horizontally disposed by being parallel with each other, in the space between which a power source arrangement section is formed. The power source arrangement section is provided for arranging power supplies of the computer therein. Through this kind of disposition structure, all motherboards in the motherboard sections can be close to the power source arrangement section as near as possible, such that a function of common usage can be achieved for both the hardware connection and the software system control. | 10-28-2010 |
20100271766 | DISPOSING STRUCTURE FOR HOT SWAPPABLE MOTHERBOARD IN INDUSTRIAL COMPUTER CHASSIS - A disposing structure of industrial computer chassis includes a chassis shell, two motherboard trays and a back plate. The interior of the chassis shell is divided into a storage unit section and a motherboard section. The interior of the storage unit section is arranged at least one storage unit, while two motherboard trays are disposed in the motherboard section. The interior of each motherboard tray is arranged a motherboard. In the motherboard trays, at least one motherboard tray is extended a wedge frame toward the storage unit section. A transfer card having a hot swapping function is arranged on the wedge frame and is arranged by inserting into the corresponding motherboard. In addition, a back plate is arranged between the storage unit section and the motherboard section. Corresponding to the wedge frame, a slot capable of a hot swapping function is arranged on the back plate. In so doing, the transfer card may be inserted into the slot, thereby, providing a hot swapping function. | 10-28-2010 |
20110026215 | SERVER MODULE - A server module includes a tray, a motherboard installed in the tray, and at least one storage device. The tray includes a port erected from a rear end of the tray, a roomage inwardly and concavely disposed on an edge of the motherboard and proximate to the port, and a socket disposed at an edge of the roomage and opposite to the port for connecting the insert roomage of the storage device, such that the storage device is disposed onto the roomage of the motherboard, and the motherboard can be used for expanding the storage device directly. | 02-03-2011 |
20110032686 | SERVER CHASSIS WITH COMMON REAR WINDOW FOR ADAPTER AND EXPANSION CARD - A structure improvement of common rear window for adapter and expansion card, arranged at a bottom seat of a server's chassis and disposed corresponding to a plug-in slot of an inside motherboard at the bottom seat, includes a rear window panel, on which a “U”-shaped notch corresponding to the plug-in slot of the motherboard is arranged, and on an upper edge of which two folded plates are provided, one side of each of which is fixed to the bottom seat, and another side of each of which is extended to an outside of the notch to form a fixing part. Two fixing parts are disposed correspondingly to each other with respect to the notch. A gold finger of a circuit board of the adapter or expansion card is plugged-in the plug-in slot of the motherboard, while a metallically connecting piece of the circuit board is fixed to the two fixing parts. | 02-10-2011 |
20110249386 | HEAT-DISSIPATING ASSEMBLY FOR SERVER - A heat-dissipating assembly for a server includes a housing in which a partitioning plate and a power supply mounted on one side of the partitioning plate are provided. The power supply includes a casing and a power-supplying module received in the casing. The heat-dissipating assembly includes a fan received in the casing and located outside the power-supplying module. The partitioning plate and the casing are respectively provided with a plurality of first heat-dissipating holes and second heat-dissipating holes. The first heat-dissipating holes and the second heat-dissipating holes are positioned to correspond to the fan. The airflow caused by the fan drives the air inside the housing to flow out of the housing via the first heat-dissipating holes and the second heat-dissipating holes. In this way, the heat-dissipating efficiency can be improved without affecting the arrangement of other electronic devices in the housing. | 10-13-2011 |
20110299254 | SCREW-LESS FIXING ASSEMBLY FOR INTERFACE CARD - A screw-less fixing assembly for an interface card having a fixing support includes a frame, a movable cover module and an elastic member. The frame has an I/O opening. One side of the I/O opening is provided with an accommodating space. A long plate of the fixing support is positioned to correspond to the I/O opening, and a short plate of the fixing support is received in the accommodating space. The movable cover module is mounted in the accommodating space. The elastic member has an elastic protrusion positioned to correspond to the short plate of the fixing support. The movable cover module is moved to drive the elastic protrusion to tightly fix the short plate of the fixing support to the frame. With this arrangement, the interface card can be rapidly detached from the frame or attached thereto without using screws. | 12-08-2011 |
20130155604 | SERVER STRUCTURE WITH SWAPPABLE TRAY - A server structure with a swappable tray includes a chassis housing, two power supply devices and a plurality of motherboard trays, and the chassis housing has two parallel motherboard areas, and each motherboard area has a power slot formed at a rear section and a plurality of tray slots at a front section, and each power slot is formed at the same position of each motherboard area, and each power supply device is plugged into each respective power slot, and each motherboard tray is in the same shape and has a motherboard, and each motherboard tray has an opening and a storage unit set installed through the opening, and each motherboard tray can be swapped and plugged into any one of the tray slots. Therefore, the motherboard tray can be installed freely at any position according to the using requirement, so as to improve the overall functionality and convenience. | 06-20-2013 |
20140204540 | SERVER WITH OPENINGS ON TWO LATERAL SIDES - A server for shortening development schedule is disclosed. A case has two tray receiving spaces. Each tray receiving space has a first opening and a second opening. Power sockets are disposed at the same position in the tray receiving spaces correspondingly. A storage unit includes a tray, a mother board and a storage component. The tray is inserted to the tray receiving space from the first opening and disposed extending to the opposite second opening. The storage unit is electrically connects with the power socket and fixed in the tray receiving space through a locking structure. | 07-24-2014 |