Patent application number | Description | Published |
20080223063 | Refrigerator with air guide duct - Disclosed is a refrigerator in which a space occupied by an evaporating dish can be minimized, evaporation efficiency of defrost water by convection-heat transfer can be improved, air can be easily exhausted in a machine room, and thus the cooling efficiency of a compressor and a condenser can be improved. The refrigerator includes: a cooling apparatus including a compressor, a condenser, and an evaporator; a blowing fan blowing air to cool at least one of the compressor and the condenser; a blowing guide duct guiding the air blown by the blowing fan to an exterior; and an evaporating dish installed in a lower portion of the blowing guide duct in order to collect and evaporate defrost water, the evaporating dish having an opened upper portion to communicate with a path of the blowing guide duct. | 09-18-2008 |
20080245093 | Apparatus for refrigeration - A refrigerator including a blowing unit optimized for a bottom type condenser. The refrigerator includes a main body having a storage compartment defined therein, a condenser mounted at the bottom of the main body, and a blowing unit to blow air that has already passed through the condenser. The blowing unit includes a centrifugal fan mounted in a machine compartment and a blowing guide member to guide air blown by the centrifugal fan to the front of the main body. Consequently, it is possible to discharge the air that has already passed through the bottom type condenser, to the front of the main body, thereby accomplishing the smooth discharge of air and reducing the power consumption necessary to blow the air. | 10-09-2008 |
20110162392 | Control method of refrigerator - A control method of a refrigerator to prevent frost from being formed in an ice making chamber. The refrigerator includes an ice making chamber refrigerant pipe to supply a refrigerant to make ice in a direct cooling manner and an ice making chamber circulation fan to create a forced air stream to circulate air in the ice making chamber. The control method includes determining whether temperature of the ice making chamber is lower than a predetermined temperature and driving the ice making chamber circulation fan in a state in which the temperature of the ice making chamber is lower than the predetermined temperature and the refrigerant flows in the ice making chamber refrigerant pipe or when flow of the refrigerant in the ice making chamber refrigerant pipe is interrupted in a state in which the temperature of the ice making chamber is lower than the predetermined temperature. | 07-07-2011 |
20110162405 | Ice making unit and refrigerator having the same - An ice making unit and a refrigerator having the same are discussed. The refrigerator includes an ice making unit arranged in the ice making compartment, to produce ice, and a refrigeration cycle comprising a refrigerant pipe to supply cooling energy to the ice making compartment. Air present in the ice making compartment is cooled while undergoing direct heat exchange with at least one of the ice making unit and the refrigerant pipe. | 07-07-2011 |
20110162406 | Refrigerator having ice making compartment with refrigerant pipe support structure - A refrigerator including a refrigeration cycle including a refrigerant pipe to supply cooling energy to an ice making compartment, an ice making tray, on which at least a portion of the refrigerant pipe is seated, a drainage duct to collect condensed water falling from the ice making tray or from at least a portion of the refrigerant pipe, and to drain the collected water, and at least one fixer to fix at least a portion of the refrigerant pipe to the ice making tray. The fixer is protruded from the drainage duct. | 07-07-2011 |
20140083127 | ICE MAKING UNIT AND REFRIGERATOR HAVING THE SAME - A refrigerator includes a body provided with a freezing compartment, a refrigerating compartment and an ice making compartment provided in the refrigerating compartment; an ice making unit including an ice making tray to produce ice in the ice making compartment; an ice storage container to store the ice made by the ice making unit; and a refrigerant pipe protruding from an interior wall of the body to supply cooling energy to the ice making compartment. A drainage duct is disposed between the ice making unit and the ice storage container adapted to prevent water drops from the ice making unit falling into the ice storage container. The drainage duct include at least one fixer configured to push the refrigerant pipe to a lower surface of the ice making tray to contact the refrigerant pipe with the lower surface of the ice making tray. | 03-27-2014 |
20150013374 | ICE MAKING UNIT AND REFRIGERATOR HAVING THE SAME - A refrigerator includes an ice making compartment, an ice making unit producing ice in the ice making compartment, and a refrigeration cycle including a refrigerant pipe to supply cooling energy to the ice making compartment. Air present in the ice making compartment is cooled while undergoing direct heat exchange with at least one of the ice making unit and the refrigerant pipe. | 01-15-2015 |
Patent application number | Description | Published |
20100127543 | Lumbar Support Device of Seat for Vehicles - A lumbar support device of a seat for a vehicle surrounds and supports the lumbar region of a passenger. In the lumbar support device, a mounting bracket is fastened to a seat back frame. A support panel is coupled to the mounting bracket through link units so as to be movable ahead of the seat back frame. Side support units are coupled to respective opposite ends of the support panel so as to be rotatable. A connection wire is connected between each of the side support units and the corresponding link unit of the support panel such that when the support panel moves forwards, the side support units surround side portions of the lumbar region of the passenger. | 05-27-2010 |
20120228910 | SEAT FOR VEHICLE - A seat for a vehicle constructed so that a side seat is provided on an opposite side of a center seat may include a first hinge shaft to which a center seat back of the center seat may be rotatably coupled for folding the center seat back forwards, a second hinge shaft to which a side seat back of the side seat may be rotatably coupled for folding the side seat back forwards, and a folding actuator assembly selectively engaging the side seat back with the center seat back, wherein the folding actuator assembly locks the center seat back to the side seat back when the side seat back may be folded, and releases the center seat back from the side seat back to fold only the center seat back when the center seat back may be folded. | 09-13-2012 |
20130113233 | SEAT APPARATUS FOR VEHICLE - A seat apparatus for a vehicle, in which a seat back may be foldable toward a seat cushion of a seat, may include a storage space provided at the bottom of a floor and storing the seat to provide a luggage space in the vehicle, a link member pivotally connected between a cushion link of the seat cushion and the storage space such that the seat may be foldable to be stored in the storage space, a locking device provided on the seat back to maintain an unfolded or folded state of the seat back, and an elastic member provided on the link member to pop up the cushion link and the seat back out of the storage space when the seat back may be unfolded. | 05-09-2013 |
20130147224 | STORING APPARATUS OF REAR SEAT FOR MULTI PURPOSE VEHICLE - A storing apparatus of a rearmost seat for a multipurpose vehicle may include a storage space provided under a floor panel, wherein the rearmost seat may be selectively stored in the storage space, and wherein the rearmost sear includes a plurality of links disposed to pivotally connect the rearmost seat with the storage space to implement a storage mode in which the seat may be moved down and received in the storage space and a sitting mode in which the seat may be drawn upward out of the storage space. | 06-13-2013 |
20140239662 | STORAGE APPARATUS FOR SEAT OF VEHICLE - A storage apparatus for a seat of a vehicle, in which the seat is stored in a storage space formed therebelow, so that it is possible to secure a wider luggage space as compare with the related art and reduce unit cost without using a separate slide rail. In addition, the storage apparatus variously uses the space of a back seat when shifted between a passenger space (seating mode) and a luggage space (luggage mode) of the multi-functional back seat, which is vertically movable and foldable. | 08-28-2014 |
20140339848 | HEADREST APPARATUS FOR MULTI-PURPOSE VEHICLE - A headrest apparatus for an MPV includes a headrest that can be automatically completely housed in a storage space in such a way as to slide without requiring a user to perform an additional operation of pushing the headrest downwards, thus being more convenient for the user. The headrest apparatus has a simple structure and a reduced size, thus reducing the weight of the vehicle. The headrest apparatus includes a headrest sliding unit, a sinking seat folding unit, and a seat support frame supporting a sinking seat on a floor of the MPV, wherein, when the sinking seat is housed in a seat storage space formed in the floor of the MPV, the upper surface of the sinking seat that is in a housed state is level with the upper surface of the floor of the MPV. | 11-20-2014 |
Patent application number | Description | Published |
20100228923 | Memory system having multiple processors - A memory system includes multiple processors. The memory system includes first and second processors, a storage device and a controller. The storage device includes one or more banks which are respectively allocated to the first processor or the second processor. The controller controls the storage device to access a plurality of banks through an interleaving method when the plurality of banks are allocated to one processor. The memory system can improve performance and power efficiency. | 09-09-2010 |
20110242131 | Image Display Devices and Methods of Displaying Image - Provided are an image display method and an image display device. The method includes: reading first layer data; reading partial data of second layer data; and blending the read first layer data and the read partial data of the second layer data and displaying the blended data. The image display device includes: a processing unit generating first and second layer data and storing the generated first and second layer data in a storage unit; and a display unit reading the first layer data and partial data of the second layer data from the storage unit, blending the read first layer data and the read partial data of the second layer data, and displaying the blended data. | 10-06-2011 |
20120096199 | BUS SYSTEM INCLUDING ID CONVERTER AND CONVERTING METHOD THEREOF - A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices. | 04-19-2012 |
20150081989 | SEMICONDUCTOR DEVICES INCLUDING APPLICATION PROCESSOR CONNECTED TO HIGH-BANDWIDTH MEMORY AND LOW-BANDWIDTH MEMORY, AND CHANNEL INTERLEAVING METHOD THEREOF - A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device. | 03-19-2015 |
Patent application number | Description | Published |
20110283080 | APPARATUS AND METHOD FOR MANAGING MEMORY - Provided is a memory management method, and an apparatus to perform the method, which achieves a shortened user waiting time in consideration of system performance. The method includes acquiring a deallocation unit used to deallocate an allocated memory area according to at least one attribute, and deallocating the allocated memory area using the deallocation unit. | 11-17-2011 |
20120084547 | METHOD AND TERMINAL OF BOOTING A COMPUTING SYSTEM - Provided is a method of booting a computing system which performs boot image transmission and device initialization in parallel. For example, using an Internal RAM and direct memory access (DMA), hardware initialization and loading of boot image from a main storage medium to a main memory are performed in parallel, thereby reducing time spent on booting. | 04-05-2012 |
20120101996 | APPARATUS AND METHOD FOR SNAPSHOT IMAGE SEGMENTATION - Provided are an apparatus to restore data, and a snapshot image segmentation apparatus and method that create a plurality of snapshot images, store the snapshot images in a storage, and load the stored snapshot images to a memory according to snapshot image loading priority. The snapshot image segmentation apparatus may includes a number-of-snapshot images deciding unit configured to decide the number of snapshot images, a segmentation unit configured to segment an entire image including data stored in a memory into one or more snapshot images, based on the number of snapshot images, and a loading priority deciding unit configured to decide snapshot image loading priority of the segmented snapshot images, based on data loading priority of the data stored in the memory. | 04-26-2012 |
20120131320 | BOOTING APPARATUS AND METHOD USING SNAPSHOT IMAGE - Provided are a booting apparatus and method using a snapshot image. A snapshot image may be divided into a plurality of blocks. Each of the blocks may be stored in a nonvolatile memory in a compressed or non-compressed format. The snapshot image may be incrementally loaded in units of the blocks during booting. The loading and decompression of the blocks may be performed in parallel. | 05-24-2012 |
20130042250 | METHOD AND APPARATUS FOR IMPROVING APPLICATION PROCESSING SPEED IN DIGITAL DEVICE - A method and apparatus for improving application processing speed in a digital device which improve application processing speed for a digital device running in an embedded environment where processor performance may not be sufficiently powerful by detecting an execution request for an application, identifying a group to which the requested application belongs, among preset groups with different priorities and scheduling the requested application according to the priority assigned to the identified group, and executing the requested application based on the scheduling result. | 02-14-2013 |
Patent application number | Description | Published |
20120001264 | ETCHANTS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided. | 01-05-2012 |
20120115293 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively. | 05-10-2012 |
20120187470 | GATE STRUCTURES - A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer. | 07-26-2012 |
20120280304 | NON-VOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions. | 11-08-2012 |
20130105880 | NONVOLATILE MEMORY DEVICES AND FABRICATING METHODS THEREOF | 05-02-2013 |
20140332875 | VERTICAL MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps. | 11-13-2014 |
Patent application number | Description | Published |
20090212861 | LOW NOISE AMPLIFIER - A low noise amplifier is provided. The low noise amplifier includes: a low noise amplifying unit amplifying an input signal; a harmonic and noise generating unit disposed in an input terminal of the low noise amplifying unit, for generating a compensating signal for compensating for an intermodulation distortion signal and a thermal noise signal of the input signal to the low noise amplifying unit; and a load unit outputting the amplified input signal generated by the low noise amplifying unit. | 08-27-2009 |
20090215421 | RF RECEIVER AND METHOD OF RECEIVING RF SIGNAL - A radio frequency (RF) receiver and a method of receiving an RF signal are provided. The RF receiver includes a low-noise amplifying unit which amplifies a received signal while restricting out-of-band interferer of the received signal, a sampling unit which performs sampling to convert the amplified signal to a discrete time domain signal, a frequency translation unit which down-converts the sampled signal into a frequency band that enables the sampled signal to be converted into a digital signal and restricts interferer from a frequency within an aliasing band according to a sampling frequency, an anti-aliasing filtering unit which prevents aliasing from the down-converted signal, a clock unit which provides the sampling unit, the frequency translation unit, and the anti-aliasing filtering unit with sampling frequencies, and an analog-digital-converter which converts the converted signal into the digital signal. | 08-27-2009 |
20090327793 | FINITE IMPULSE RESPONSE (FIR) FILTER WITHOUT DECIMATION - Provided is a discrete signal finite impulse response (FIR) filter and a filter set in which a plurality of FIR filter units are connected in a cascade structure to remove down-sampling by decimation, in order to improve the attenuation characteristics of a FIR filter, such as, for example, a switched capacitor filter. The FIR filter includes a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample. Each sub block being in a state among a number of possible states including N charging states for storing the received sample, a transfer state for outputting the stored sample and a reset state for operation initialization. The N charging states, the transfer state and the reset state are changed sequentially in response to the clock signals. | 12-31-2009 |
Patent application number | Description | Published |
20110129376 | PULSE PRESSURE DECREASING TYPE VARIABLE OIL PUMP - A pulse pressure decreasing type variable oil pump may include an inner chamber rotatably receiving a vane therein, wherein an outer ring rotatably covers the inner chamber, a housing enclosing the outer ring, the inner chamber, and the vane therein and forming a narrow section between the housing and the outer ring to increase pressure of oil flowing therein, and a pressure chamber grooved in an inner side of the housing and fluid-communicating the inner chamber with the narrow section. | 06-02-2011 |
20120076683 | Structure of Variable Oil Pump - A variable oil pump includes an inlet connected to supply oil into the housing of the variable oil pump an arc-shaped intake space formed in the housing to be connected to a pumping space between veins mounted on a rotor in the variable oil pump; and a buffer space having a large cross-sectional area than inlet and connected with inlet and intake space, such that it is possible to reduce pulse noise generated in the variable oil pump by reducing intake resistance and vortex which are generated in sucking oil at the intake side of the variable oil pump. | 03-29-2012 |
20140165975 | EXHAUST GAS RECIRCULATION VALVE FOR VEHICLE - An exhaust gas recirculation valve for a vehicle may include a housing having a flow path through which an exhaust gas flows, a shaft installed in the housing to be rotatable, a flap valve provided to be rotatable about the shaft and configured to open and close the flow path, a bushing provided on the shaft, an anti-wear washer installed on the shaft between the flap valve and the bushing, and a spring means installed on the shaft and configured to elastically support the bushing. | 06-19-2014 |
20140182567 | EXHAUST GAS RECIRCULATION VALVE DEVICE FOR VEHICLE - An exhaust gas recirculation valve device for a vehicle includes a valve housing having an exhaust gas inlet port and an exhaust gas outlet port, a flap valve rotatably mounted on the valve housing to open and close the exhaust gas outlet port, and a valve shaft fitted to penetrate the flap valve and coupled to the flap valve by electron beam welding to rotate integrally with the flap valve. | 07-03-2014 |
Patent application number | Description | Published |
20090016131 | BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing the bit line sense amplifier circuit of the semiconductor memory device from floating, and preventing or substantially reducing a coupling effect, thereby providing a precise data sensing and amplification operation. | 01-15-2009 |
20090097349 | Row active time control circuit and a semiconductor memory device having the same - A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal. | 04-16-2009 |
20100106900 | Semiconductor memory device and method thereof - A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory. | 04-29-2010 |
Patent application number | Description | Published |
20080244835 | Apparatus and method for machine washing - Disclosed is an apparatus and method for machine washing that includes a sterilizer capable of continuously exhibiting antibiotic and sterilization functions during washing and rinsing processes and reducing the consumption amount of Ag. The washing machine comprises a water reservoir to contain washing water, a sterilizer sterilizing the washing water through an electrolysis process, and a circulator circulating the washing water in the sterilizer. | 10-09-2008 |
20090293204 | Washing machine and method of washing drum - Disclosed are a washing machine and a method of controlling the same. The washing machine includes a drum; a washing device to spray water to perform washing of an outer surface of the drum; and a control unit controlling the washing of the outer surface of the drum such that the washing of the outer surface of the drum is performed during a washing or rinsing cycle. The washing machine does not need to be disassembled to wash the drum and tub and thus is easily washed and has the ribs extended in a same direction of an extension direction of the flange shaft to increase the strength of the flange shaft and thus forms channels of water flowing on the flange shaft and reduces the remaining of contaminants on the flange shaft in the washing or rinsing cycle to enhance the washability of the flange shaft. | 12-03-2009 |
20100000574 | CONTROL METHOD OF WASHING MACHINE - A control method of a washing machine is capable of safely achieving a tub washing operation control with low power consumption. At the time of performing tub washing, water of which the amount is decided depending on a volume inside a drum and a volume inside a water tub is supplied to the water tub, and the rotation speed of the drum is controlled to be inversely proportional to the volume of the supplied water, thereby efficiently controlling a tub washing operation with low power consumption. Also, the rotation state of the drum is controlled, at the time of performing the tub washing, to maintain the temperature of a motor or a printed circuit board (PCB) to be a predetermined level or less, thereby safely controlling a tub washing operation with low power consumption. In addition, it is determined whether the revolutions per minute (RPM) of the drum rotating at the tub washing operation belong to a resonance band, and the RPM are controlled such that the RPM deviate from the resonance band, thereby achieving a tub washing operation procedure with small noise and vibration. | 01-07-2010 |
20130112225 | DISH WASHER AND CONTROL METHOD THEREOF - A dish washer includes a washing tub accommodating a detergent containing a first enzyme activated at an active temperature range and a second enzyme activated at another active temperature range differing from the active temperature range of the first enzyme, and wash water in which the detergent is dissolved, a heating unit heating wash water, and a controller controls driving of the heating unit such that the temperature of wash water is maintained within the active temperature range of the first enzyme for a first designated time, and controls driving of the heating unit such that the temperature of wash water is maintained within the active temperature range of the second enzyme for a second designated time, when the first designated time has elapsed. | 05-09-2013 |
20130145562 | DRUM WASHING MACHINE AND WASHING METHOD THEREOF - A drum washing machine and washing method are provided. The washing machine directly sprays water to laundry inside the drum through a nozzle unit. The method includes passing some water through a detergent container and directly spraying some water to the inside of a drum through a nozzle unit such that a high concentration of detergent bubbles is generated while applying a force to the laundry. The washing machine includes a cabinet, a tub inside the cabinet, a drum inside the tub, a door on the cabinet, a diaphragm, and a nozzle unit installed so interference with the door is avoided and to receive water directly from an external source to spray water inside the drum during a washing cycle and a rinsing cycle. The nozzle unit adjusts water jetting according to a displacement of an actuator installed inside the nozzle unit. | 06-13-2013 |
20130152969 | DISHWASHER AND METHOD FOR CONTROLLING THE SAME - A dishwasher, in which a reservoir provided with an electrolyzer is connected to a water collector via a flow path change valve, and wash water in the reservoir is electrolyzed by the electrolyzer during non-operation of the wash water, to generate sterilizing water and to circulate the sterilizing water into the dishwasher, thereby achieving an enhancement in sterilizability of the dishwasher. A method for controlling a dishwasher makes it possible to suppress propagation of microorganisms left in the dishwasher and to remove organic substances, using a sterilizing agent or high-temperature water. It is also possible to reduce generation of offensive odor caused by decomposition of bacteria, through a reduction in the amount of bacteria in the dishwasher. Since sterilization of the dishwasher is automatically carried out, enhanced user convenience is provided. | 06-20-2013 |
20140298835 | DEODORIZING FILTER AND REFRIGERATOR HAVING THE SAME - A deodorizing filter including at least one deodorizing member to adsorb odor particles contained in fluid. The deodorizing member includes a substrate having plural pass-through pores to allow passage of the fluid, an adherent material applied to a surface of the substrate, and plural porous deodorizer materials fixed to the surface of the substrate by the adherent material to adsorb the odor particles. The deodorizing filter more effectively deodorizes interior air of a refrigerator owing to an increased contact area between interior air of the refrigerator and the deodorizer materials of the deodorizing filter. | 10-09-2014 |
Patent application number | Description | Published |
20120246352 | DATA PROCESSING SYSTEMS FOR AUDIO SIGNALS AND METHODS OF OPERATING SAME - A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer. | 09-27-2012 |
20120246353 | AUDIO DEVICE AND METHOD OF OPERATING THE SAME - An audio device and a method of operating the same are provided. The audio device includes a storage unit, a first memory and a second memory, a hardware decoder, a software decoder, a first direct memory access (DMA) block, a second DMA block, and a controller. The controller converts the audio device from an ultra low power mode in which the first PCM information is transmitted to an audio interface buffer through the first memory, the hardware decoder, and the first DMA block or a low power mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the first DMA block to a normal mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the second DMA block. | 09-27-2012 |
Patent application number | Description | Published |
20120120082 | Level Shifter, System-on-Chip Including the Same, and Multimedia Device Including the Same - Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node. | 05-17-2012 |
20120185747 | METHODS OF ENCODING/DECODING FOR ERROR CORRECTION CODE UTILIZING INTERDEPENDENT PORTIONS OF CODEWORDS AND RELATED CIRCUITS - A method of encoding/decoding data for storage in and retrieval from a flash memory device, can be provided by generating a first error correction code on a combination of first user data to be stored in a first logical unit of storage in the flash memory device and padding data that is derived from second user data and an associated second error correction code stored in a second logical unit of storage in the flash memory device that is directly adjacent to the first logical unit of storage. The first user data and the first error correction code can be stored in the first logical unit of storage. | 07-19-2012 |
20150048521 | SEMICONDUCTOR PACKAGE - According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively. The first and second jumper chips are spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction. The second semiconductor package may include a second package substrate and a logic chip on the second package substrate. The first semiconductor package may be on the second semiconductor package. | 02-19-2015 |
Patent application number | Description | Published |
20120314970 | IMAGE PROCESSING DEVICE, PROCESSING METHOD THEREOF, AND IMAGE PROCESSING SYSTEM HAVING THE SAME - An image processing device is provided. The image processing device includes a weighted low-pass filter which performs weighted low-pass filtering on illumination of sub-sampled pixel signals, and an illumination interpolation circuit which compares illumination of the weighted low-pass filtered pixel signals with illumination of current pixel signals and performs interpolation while applying a weight to illumination of the weighted low-pass filtered pixel signals according to the comparison result. | 12-13-2012 |
20130219208 | METHOD OF CORRECTING A DUTY RATIO OF A DATA STROBE SIGNAL - A method of correcting a duty ratio of a data strobe signal is provided. By the method, a duty ratio of a data strobe signal output from a semiconductor memory device is detected and a duty ratio of a clock signal input to the semiconductor memory device is adjusted based on the duty ratio of the data strobe signal. | 08-22-2013 |
20140025930 | MULTI-CORE PROCESSOR SHARING LI CACHE AND METHOD OF OPERATING SAME - A multi-core processor includes first processor core including a first instruction fetch unit and out-of-order execution data units, a second processor core including a second instruction fetch unit and in-order execution data units, and a shared-level 1 cache including a level 1-instruction cache shared between the first instruction fetch unit and the second instruction fetch unit and a level 1-data cache shared between the out-of-order execution data units and the in-order execution data. | 01-23-2014 |
20140195742 | SYSTEM ON CHIP INCLUDING MEMORY MANAGEMENT UNIT AND MEMORY ADDRESS TRANSLATION METHOD THEREOF - A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets. | 07-10-2014 |
20140268979 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups. | 09-18-2014 |
Patent application number | Description | Published |
20130089631 | COMPOSITION CONTAINING COLORED-BEAN EXTRACTS - The present invention relates to an antithrombotic composition containing a fraction of a colored-bean extract. The antithrombotic composition is highly useful for the treatment of diseases of the circulatory system, including cardiovascular disease, cerebrovascular disease, arteriosclerosis, hypertension and diabetes, which are caused by thrombosis. | 04-11-2013 |
20130095197 | COMPOSITION CONTAINING COLORED-BEAN EXTRACT - The present invention relates to an antithrombotic composition comprising a colored-bean extract or a fraction of the extract. The antithrombotic composition is highly useful for the treatment of diseases of the circulatory system, including cardiovascular disease, cerebrovascular disease, arteriosclerosis, hypertension and diabetes, which are caused by thrombosis. | 04-18-2013 |
20130158025 | NOVEL COMPOUND ACTING AS A CANNABINOID RECEPTOR-1 INHIBITOR - Disclosed is a novel compound acting as a cannabinoid receptor 1 inhibitor, a prodrug thereof, an isomer thereof, a pharmaceutically acceptable salt thereof, a hydrate thereof or a solvate thereof. The novel compound or the like is useful for preventing or treating diseases mediated by the cannabinoid receptor-1. | 06-20-2013 |
20140011881 | NOVEL COMPOUNDS, ISOMER THEREOF, OR PHARMACEUTICALLY ACCEPTABLE SALTS THEREOF AS VANILLOID RECEPTOR ANTAGONIST; AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME - This present disclosure relates to novel compounds, isomer thereof or pharmaceutically acceptable salts thereof as vanilloid receptor (Vanilloid Receptor 1; VR1; TRPV1) antagonist; and a pharmaceutical composition containing the same. | 01-09-2014 |
Patent application number | Description | Published |
20090152614 | NAND flash memory device having a contact for controlling a well potential - A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines. | 06-18-2009 |
20100178773 | METHOD OF FORMING SEMICONDUCTOR DEVICES EMPLOYING DOUBLE PATTERNING - A first material film is formed on a substrate. Linear second material film patterns are formed on the first material film. Spacer patterns are formed on sidewalls of the second material film patterns, and the second material film patterns are removed to expose portions of the first material film between the spacer patterns. The exposed portions of the first material film are removed to form first material film patterns. Third material film patterns are formed in trenches defined by the first material film patterns. Adjacent first portions of the second material film patterns proximate ends of the second material film patterns are separated by a distance less than twice a width of the individual spacer patterns. In some embodiments, the distance separating the adjacent first portions of the second material film patterns is greater than a minimum feature size, and a width of the individual spacer patterns is approximately equal to the minimum feature size. | 07-15-2010 |
20110001243 | SEMICONDUCTOR DEVICE INCLUDING DUMMY - A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug. | 01-06-2011 |
20140159246 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 06-12-2014 |
20140210095 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 07-31-2014 |
Patent application number | Description | Published |
20100309404 | LIQUID CRYSTAL DISPLAY MODULE FOR PORTABLE TERMINAL - A Liquid Crystal Display (LCD) module for a portable terminal having a display unit is provided. The LCD module includes a reinforcement plate having a bottom surface and a side surface bent to extend from the bottom surface, a backlight unit coupled to an upper part of the reinforcement plate, a frame insert molded to the reinforcement plate and coupled to an edge of the backlight unit, and an LCD panel coupled to an upper part of the backlight unit, wherein the side surface of the reinforcement plate extends from the bottom surface to have a height greater than the combined height of the coupled LCD panel and the backlight unit, and further wherein the frame is formed to have a height not extending up to the LCD panel. | 12-09-2010 |
20110216489 | LIQUID CRYSTAL DISPLAY MODULE FOR PORTABLE TERMINAL - A Liquid Crystal Display (LCD) module for use in a portable terminal is provided. The LCD module includes a reinforcement plate of a metal material having a bottom surface, and a side surface bent and extended at a substantially constant height along an edge from the bottom surface, a backlight unit laminated onto an upper part of the reinforcement plate, and having a frame of a synthetic resin material that is formed along an edge to insert-mold the reinforcement plate, and an LCD panel fixed by a double sided tape at an upper part of the backlight unit. A portion of the side surface of the reinforcement plate is sequentially twice bent back onto itself on the outside of the reinforcement plate such that its end has a substantially constant width in contact with the bottom surface of the reinforcement plate. | 09-08-2011 |
20120230037 | LIGHTING DEVICE AND DISPLAY DEVICE HAVING THE SAME - A display device and a lighting device are provided. The display device includes a display element for outputting an image according to a provided image signal, a frame disposed on a rear surface of the display element, and a reflection layer formed on the frame and positioned between the display device and the frame, the reflection layer being a coating layer formed using a paint including at least one of silver and aluminum. When the backlighting device of the display device is configured, a reflection plate where deposition films and a reflection layer made of a metal component are deposited is not required and the reflection layer is formed on the frame by using a paint having at least one of silver and aluminum as its main components, thereby simplifying a manufacturing process, and contributing to reducing the thickness of the display device. | 09-13-2012 |
20130155348 | LIQUID CRYSTAL DISPLAY MODULE FOR PORTABLE TERMINAL - A portable terminal including a Liquid Crystal Display (LCD) module is provided. The LCD module includes a reinforcement plate having a bottom surface and a side surface bent to extend from the bottom surface, wherein the reinforcement plate comprises a plurality of molding holes provided in a boundary portion between the bottom surface and the side surface of the reinforcement plate, a backlight unit coupled to an upper part of the reinforcement plate, a frame molded to the reinforcement plate, and an LCD panel coupled to an upper part of the backlight unit, wherein each of the plurality of molding holes extends into both the bottom surface and the side surface from the boundary portion between the bottom surface and the side surface. | 06-20-2013 |
Patent application number | Description | Published |
20130010223 | LIQUID CRYSTAL DISPLAY BACKLIGHT DEVICE - A liquid crystal display backlight device for reducing a thickness of a terminal is provided. The liquid crystal display backlight device includes a backlight unit disposed at a lower part of a liquid crystal display module, a set bracket for mounting while enclosing the backlight unit, and a liquid crystal display Flexible Printed Circuit Board (FPCB) folded from the liquid crystal display module to a rear surface of the set bracket. Therefore, a thickness and width of the liquid crystal display backlight device can further be reduced and thus a user can easily carry the liquid crystal display backlight device. Further, rigidity of the set bracket can be prevented from being weakened. | 01-10-2013 |
20130021573 | USER TERMINAL AND DISPLAY PANEL THEREOF - A user terminal and a display panel thereof are provided. The user terminal includes a touch panel for detecting a touch generated in a surface thereof, and a display panel comprising glass plates, each disposed at a lower surface of the touch panel and comprising an active area for displaying an image and a black matrix at an edge area of the active area, a liquid crystal layer between the glass plates, and photo spacers mounted on one of the glass plates and received in the liquid crystal layer, for supporting flow of liquid crystals in the liquid crystal layer and for sustaining a gap between the glass plates, wherein the photo spacers comprise dummy photo spacers disposed at a black matrix between the glass plates for inverting a flow direction of liquid crystals advancing toward the black matrix from the active area. Therefore, liquid crystals flow more smoothly. | 01-24-2013 |
20130057485 | USER TERMINAL AND DISPLAY DEVICE THEREOF - A user terminal and a display device thereof are provided. The display device includes a display panel including a glass plate for displaying an image by outputting light, and a polarizing plate attached to both a top surface and a bottom surface of the glass plate for exposing an edge portion of the glass plate, a cover window mounted on the display panel for transmitting the light, an adhesive sheet interposed between the display panel and the cover window and for adhering the cover window at the edge portion of the glass plate. The user terminal can be formed to have a small thickness and size, and light is shielded from being leaked to the outside of the user terminal via an edge portion of the display panel in the user terminal. | 03-07-2013 |
20130113733 | DISPLAY PANEL AND MOBILE DEVICE WITH THE SAME - A display panel and a mobile device with the display panel are provided. The display panel includes a display module and a back light unit. The display module includes a glass substrate for displaying videos by controlling a transmittance and a color of light, an upper polarizer that is placed on an upper side of the glass substrate, and a lower polarizer that is placed on a lower side of the glass substrate and exposes an edge of the glass substrate. The back light unit includes: a light source, a light waveguide that is placed on a lower side of the lower polarizer and that transfers light from the light source to the lower polarizer, and a Flexible Printed Circuit Board (FPCB), which is placed at the edge of the glass substrate exposed by the lower polarizer, that supplies electric power to the light source, and that reflects light from the light source to the light waveguide. The display panel is cost-effective and has high optical efficiency. | 05-09-2013 |
Patent application number | Description | Published |
20100314760 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land. | 12-16-2010 |
20110018119 | Semiconductor packages including heat slugs - A semiconductor package may include at least one semiconductor chip mounted on a substrate, a molding layer adapted to mold the at least one semiconductor chip, a heat slug, on the molding layer, having a structure in which a dielectric is provided between conductors, and a through mold via electrically connecting the heat slug to the substrate. | 01-27-2011 |
20130005092 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land. | 01-03-2013 |
20140328031 | DISPLAY APPARATUS - Provided is a display apparatus. The display apparatus includes a display panel, a flexible circuit film having a rear surface connected to the display panel, and a front surface opposite to the rear surface, the front surface having a chip mounted thereon, and a first lead bonding portion electrically connecting the chip to the display panel. The first lead bonding portion includes a first portion connected to the chip and overlying a portion of the flexible circuit film, a second portion passing through the flexible circuit film, and a third portion disposed between the flexible circuit film and the display panel on the rear surface of the flexible circuit film, where the third portion overlaps the first portion. | 11-06-2014 |
Patent application number | Description | Published |
20090322362 | Test pad structure, a pad structure for inspecting a semiconductor chip and a wiring subtrate for a tape package having the same - A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row. | 12-31-2009 |
20100276189 | SEMICONDUCTOR PACKAGE INCLUDING POWER BALL MATRIX AND POWER RING HAVING IMPROVED POWER INTEGRITY - In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states. | 11-04-2010 |
20110233755 | Semiconductor Housing Package, Semiconductor Package Structure Including The Semiconductor Housing Package, And Processor-Based System Including The Semiconductor Package Structure - A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system. | 09-29-2011 |
20120068349 | TAPE PACKAGE - A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance. | 03-22-2012 |
20120085383 | SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME - A solar cell module having a reduced thickness using a flip-chip approach includes a transparent substrate, a transparent electrode interconnection disposed on the transparent substrate, and a plurality of solar cells disposed on the transparent electrode interconnection, each solar cell having at least one protrusion formed on one surface of the solar cell, the protrusion being bonded to the transparent electrode interconnection. | 04-12-2012 |
20120085393 | SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SAME - A solar cell module includes a circuit board, a plurality of solar cells disposed on a first surface of the circuit board, a plurality of metal terminals formed on the first surface of the circuit board, and a plurality of wires electrically connecting the plurality of solar cells and the metal terminals. The circuit board has a second surface opposite to the first surface, the rear surface comprising openings corresponding to the metal terminals, the openings exposing the metal terminals to an exterior of the solar cell module, thus forming contact terminals for the solar cell module. | 04-12-2012 |
20120091468 | SEMICONDUCTOR DEVICE WITH INTERPOSER AND METHOD MANUFACTURING SAME - A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip | 04-19-2012 |
20120126431 | SEMICONDUCTOR PACKAGE - A semiconductor package having improved EMI and crosstalk characteristics is provided. The semiconductor package includes a semiconductor package including a substrate, at least one first semiconductor chip formed on a top surface of the substrate and electrically connected to the substrate, and at least one second semiconductor chip formed on a top surface of the first semiconductor chip and electrically connected to the first semiconductor chip, wherein first and second conductive layers are formed on the top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the first conductive layer and the second conductive layer are connected to a ground portion. | 05-24-2012 |
20120138968 | SEMICONDUCTOR PACKAGE AND DISPLAY PANEL ASSEMBLY HAVING THE SAME - Provided are a semiconductor package with a reduced lead pitch, and a display panel assembly having the semiconductor package. The semiconductor package includes a film having a hole formed therein, a plating pattern formed under the film and forming a wire; a semiconductor chip placed in the hole and electrically connected to the plating pattern; and a first passivation layer formed at a side opposite to the semiconductor chip about the plating pattern and protecting the plating pattern. | 06-07-2012 |
20140054793 | Chip on Film (COF) Substrate, COF Package and Display Device Including the Same - A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film. | 02-27-2014 |
20140246687 | CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME - A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads. | 09-04-2014 |
20140327148 | CHIP ON FILM PACKAGE INCLUDING DISTRIBUTED VIA PLUGS - A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second leads on the first surface of the film substrate, the second leads having a second length larger than the first length, first via plugs penetrating the film substrate and connected to first ends of the first leads, and second via plugs penetrating the film substrate and connected to first ends of the second leads, and first connection leads on a second surface of the film substrate facing the first surface, the first connection leads having first ends connected to the first via plugs, and second connection leads on the second surface of the film substrate, the second connection leads having first ends electrically connected to the second via plugs. | 11-06-2014 |
Patent application number | Description | Published |
20110062537 | Magnetic Memory Devices - A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer. | 03-17-2011 |
20110189851 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern. | 08-04-2011 |
20110260272 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer. | 10-27-2011 |
20110303996 | MAGNETIC MEMORY DEVICES - A magnetic memory device includes a reference magnetic layer having a fixed magnetization direction, a tunnel barrier layer on the reference magnetic layer, a free layer having a variable magnetization direction on the tunnel barrier layer opposite the reference magnetic layer, and a magnetization reversal auxiliary layer on the free layer. The magnetization reversal auxiliary layer has a fixed magnetization direction that is substantially perpendicular to a plane along an interface between the tunnel barrier layer and the reference layer. The magnetization reversal auxiliary layer may be directly on the free layer, or an exchange coupling control layer may be provided between the magnetization reversal auxiliary layer and the free layer. | 12-15-2011 |
20120018824 | MAGNETIC MEMORY LAYER AND MAGNETIC MEMORY DEVICE INCLUDING THE SAME - A magnetic memory layer and a magnetic memory device including the same, the magnetic memory layer including a first seed layer; a second seed layer on the first seed layer, the second seed layer grown according to a <002> crystal direction with respect to a surface of the first seed layer; and a main magnetic layer on the second seed layer, the main magnetic layer grown according to the <002> crystal direction with respect to a surface of the second seed layer. | 01-26-2012 |
20120292724 | MAGNETIC DEVICE - A magnetic tunnel junction element is provided. The magnetic tunnel junction element has first magnetic layer and second magnetic layer formed adjacent, e.g., on lower and upper portions of an insulating layer, respectively and each having a perpendicular magnetic anisotropy, a magnetic field adjustment layer formed on the second magnetic layer and having a perpendicular magnetic anisotropy, and a bather layer formed between the magnetic field adjustment layer and the second magnetic layer. The second magnetic layer and the magnetic field adjustment layer are magnetically decoupled from each other. | 11-22-2012 |
20130234269 | MAGNETIC MEMORY DEVICES INCLUDING MAGNETIC LAYERS SEPARATED BY TUNNEL BARRIERS - A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer. | 09-12-2013 |
20130285178 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the fist vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer. | 10-31-2013 |
20140353784 | MAGNETIC MEMORY DEVICE - A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer. | 12-04-2014 |
Patent application number | Description | Published |
20110292261 | ANALOG-TO-DIGITAL CONVERTER AND DEVICES INCLUDING THE SAME - An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal. | 12-01-2011 |
20120007653 | DATA TRANSMISSION DEVICE AND IMAGE SENSOR SYSTEM USING THE SAME - A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain. | 01-12-2012 |
20120033097 | COUNTER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER (ADC) INCLUDING A COUNTER CIRCUIT, IMAGE SENSOR INCLUDING COUNTER CIRCUIT AND/OR ADC, SYSTEMS ASSOCIATED THEREWITH, AND METHOD ASSOCIATED THEREWITH - In one embodiment, the counter circuit is associated with a pixel array and includes a plurality of counting circuits. Each counting circuit is configured to receive an associated input signal, and each input signal is associated with a different column of the pixel array. A first of the plurality of counting circuits is configured to count based on the associated input signal. Each subsequent counting circuit in the plurality of counting circuits is configured to count based on a difference between the associated input signal and the input signal associated with a preceding counting circuit. | 02-09-2012 |
20120097840 | ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR INCLUDING SAME - An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval. | 04-26-2012 |
20120113286 | Analog to Digital Converters, Image Sensor Systems, and Methods of Operating the Same - An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage. | 05-10-2012 |
20120140089 | IMAGE SENSOR AND CAMERA SYSTEM HAVING THE SAME - An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio. | 06-07-2012 |
20130009800 | DUAL-MODE COMPARATOR AND ANALOG TO DIGITAL CONVERTER HAVING THE SAME - A dual-mode comparator may include an object voltage input unit that generates a first current flowing through a first path and a second current flowing through a second path based on a first object voltage and a second object voltage, a current mirror unit that performs a current-mirror operation for the first path and the second path to output a comparison voltage at an output terminal, a bias unit that generates a bias current corresponding to a sum of the first current and the second current, and a mode switching unit that controls the current mirror unit to have a first structure in an auto-zero mode and that controls the current mirror unit to have a second structure in a comparison mode. | 01-10-2013 |
20130141619 | IMAGE SENSORS AND IMAGE PROCESSING DEVICES INCLUDING THE SAME - An image sensor may include a photodiode configured to convert an optical signal into photogenerated charge, a sensing node adjacent to the photodiode and configured to sense the photogenerated charge, a read-out circuit configured to convert the photogenerated charge into an electrical signal and to output the electrical signal through an output line, and/or at least one capacitor formed between the sensing node and a conversion gain control line. The conversion gain control line corresponding to the at least one capacitor may be selectively connected to a ground line or the output line based on at least one control signal. | 06-06-2013 |
20140145067 | IMAGE SENSOR AND SYSTEM INCLUDING THE SAME - An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time. | 05-29-2014 |
20140240569 | IMAGE SENSOR - An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to n | 08-28-2014 |