Patent application number | Description | Published |
20140253101 | SYSTEM AND METHOD OF MEASURING REAL-TIME CURRENT - A system and method of measuring real-time current is disclosed. The method includes calibrating a voltage measurement device. Calibrating includes measuring a real-time voltage difference between a first measurement node located proximate a first connector on a motherboard and a second measurement node located proximate a second connector on a power supply unit (PSU), the first and the second connectors coupled to provide power to the motherboard. Calibrating further includes averaging the real-time voltage difference for a plurality of measurements; computing a resistance of the coupling based at least on a long-duration averaged current from the PSU and the averaged real-time voltage difference, the resistance varying over time; and reporting the resistance of the coupling to the voltage measurement device. The method also includes measuring a real-time current of the PSU at the voltage measurement device based at least on the resistance of the coupling and the real-time voltage difference. | 09-11-2014 |
20150113294 | SYSTEMS AND METHODS FOR MANAGING A VOLTAGE REGULATOR - A voltage regulator may comprise a high-side switch and a low-side switch for delivering electrical current to the at least one information handling resource, a high-side driver configured to drive a high-side driving voltage for regulating a first electrical current of the high-side switch, a low-side driver configured to drive a low-side driving voltage for regulating a second electrical current of the low-side switch, and a control circuit configured to operate the at least one voltage regulator in both of a fixed dead time mode and an adaptive dead time mode. | 04-23-2015 |
20150323572 | SYSTEM AND METHOD OF MEASURING REAL-TIME CURRENT - A system and method of measuring real-time current is disclosed. The method includes calibrating a voltage measurement device. Calibrating includes measuring a real-time voltage difference between a first measurement node located proximate a first connector on a motherboard and a second measurement node located proximate a second connector on a power supply unit (PSU), the first and the second connectors coupled to provide power to the motherboard. Calibrating further includes averaging the real-time voltage difference for a plurality of measurements; computing a resistance of the coupling based at least on a long-duration averaged current from the PSU and the averaged real-time voltage difference, the resistance varying over time; and reporting the resistance of the coupling to the voltage measurement device. The method also includes measuring a real-time current of the PSU at the voltage measurement device based at least on the resistance of the coupling and the real-time voltage difference. | 11-12-2015 |
20150370300 | METHODS AND SYSTEMS FOR CALIBRATION OF VOLTAGE REGULATOR SYSTEMS WITH MULTIPLE TYPES OF POWER STAGES - Methods and systems are disclosed that may be employed to enable multi-phase voltage regulator (VR) system calibration during the development phase of a multi-phase VR system so as to meet defined accuracy targets and, in one example, to avoid the need for system level calibration in a production environment. The disclosed systems and methods may be further implemented to enable use of multiple sources for and types of integrated power stages (IPstages) in a common multi-phase VR system configuration while still achieving the required current sense accuracy, thus reducing or substantially eliminating continuity of supply (COS) concerns. The disclosed methods and systems may also be implemented to improve accuracy of current sense in a manner that improves VR system performance, power saving and reliability. | 12-24-2015 |
20150372597 | METHODS AND SYSTEMS FOR IMPROVING LIGHT LOAD EFFICIENCY FOR POWER STAGES OF MULTI-PHASE VOLTAGE REGULATOR CIRCUITS - Methods and systems are disclosed that may be employed to improve efficiency of smart integrated power stages (IPstages) of multi-phase VR systems while operating under relatively light, ultra-light, or partial or reduced loads. The disclosed methods and systems may be implemented to improve VR system light load efficiency by providing and enabling reduced power IPstage operating modes in one or more smart IPstage/s of a VR system, and by enabling state transition between IPstage active and reduced power operating modes such as IPstage standby and IPstage hibernation modes. | 12-24-2015 |
20160094122 | METHODS AND SYSTEMS FOR IMPROVING LIGHT LOAD EFFICIENCY FOR POWER STAGES OF MULTI-PHASE VOLTAGE REGULATOR CIRCUITS - Methods and systems are disclosed that may be employed to improve efficiency of smart integrated power stages (IPstages) of multi-phase VR systems while operating under relatively light, ultra-light, or partial or reduced loads. The disclosed methods and systems may be implemented to improve VR system light load efficiency by providing and enabling reduced power IPstage operating modes in one or more smart IPstage/s of a VR system, and by enabling state transition between IPstage active and reduced power operating modes such as IPstage standby and IPstage hibernation modes. | 03-31-2016 |
20160105101 | SYSTEMS AND METHODS FOR MEASURING POWER SYSTEM CURRENT USING OR-ING MOSFETS - In accordance with embodiments of the present disclosure, a power supply unit may include one or more stages including an output stage configured to generate a direct-current output voltage at an output of the power supply, an OR-ing metal-oxide-semiconductor field effect transistor (MOSFET) coupled between the output stage and the output, and a controller. The controller may be configured to measure a signal indicative of a voltage associated with the OR-ing MOSFET and determine an estimated output current of the power supply based on the signal. | 04-14-2016 |
Patent application number | Description | Published |
20090154603 | Weather band radio having digital frequency control - In one embodiment, the present invention includes a digital mixer to receive and digitally mix incoming weather band radio data with a control signal, a digital demodulator to demodulate the data to obtain a demodulated signal, and a digital feedback loop coupled between the demodulator and the digital mixer. The digital feedback loop includes a loop filter to receive the demodulated signal and to generate a filtered output and a fine tune controller to receive the filtered output and a frequency control signal and to generate the control signal based on them. In this way, audible artifacts caused by a frequency step change occurring in an analog front end to which the digital circuitry is coupled can be reduced or removed. | 06-18-2009 |
20090154606 | Combining soft decisions in a weather band radio - According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data. | 06-18-2009 |
20100167680 | Controllable image cancellation in a radio receiver - In one embodiment, a receiver includes parallel paths for signal channel processing and image channel processing. The paths may include a mixer to receive an intermediate frequency (IF) signal and to downconvert the IF signal to a channel baseband signal, a filter to generate a filtered channel value, a combiner to combine the channel baseband signal with a filtered channel value from the other path to obtain a channel path output, in addition to one or more controllers to generate a step control signal and update a weighting of the filters based at least in part on the step control signal. | 07-01-2010 |
20110044414 | Mitigating Radio Receiver Multipath Noise - In one embodiment, a method for processing radio frequency signals includes estimating an average value of a demodulated signal and a noise signal, both obtained from a radio frequency signal, estimating a noise floor based on the noise signal, generating a blend control signal based on the average values and the noise floor, and blending at least two path signals based on the blend control signal to obtain a blended signal. This blended signal may be output for further processing when multipath noise is detected. | 02-24-2011 |
20110261912 | Performing Impulse Blanking Based On Blocker Information - One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankets may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured. | 10-27-2011 |
20120099680 | Combining Soft Decisions In A Weather Band Radio - According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data. | 04-26-2012 |
20130003903 | Performing Impulse Blanking Based On Blocker Information - One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankers may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured. | 01-03-2013 |
20130260707 | Controlling Filter Bandwidth Based On Blocking Signals - In one embodiment, a method includes determining in a controller of a radio receiver whether at least one blocker signal is present in a blocking spectrum surrounding a desired radio channel. If no blocker signal is present, a channel filter of a signal processing path of the radio receiver may be controlled to operate at a first bandwidth. If a first blocker signal is present, the channel filter may be controlled to operate at a second bandwidth less than the first bandwidth. If the first blocker signal and a second blocker signal are present on opposing sides of the desired radio channel, the channel filter may be controlled to operate at a third bandwidth less than the second bandwidth, when a beating signal based on the first and second blocker signals is greater than a threshold level. | 10-03-2013 |
20140370832 | Efficient Dual Channel Conversion In A Multi-Band Radio Receiver - In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands. | 12-18-2014 |
20150341063 | Updating A Filter Of An Equalizer - In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter. | 11-26-2015 |
20150365117 | Radio Frequency (RF) Receivers Having Whitened Digital Frame Processing And Related Methods - Radio frequency (RF) receivers having whitened digital frame processing and related methods are disclosed. Disclosed embodiments whiten frequency domain interference generated periodic current pulses from by digital frame processing by applying a variable time delay to the frame control signals that initiate digital frame processing. For one embodiment, the variable time delay is achieved by waiting a variable number of digital clock cycles for each digital frame processing cycle. Still further, a variable number of no operation (NO-OP) cycles can be performed at the beginning of each frame processing cycle to provide the variable time delay for the variable number of digital clock cycles. Other variable time delay techniques could also be utilized while still taking advantage of the whitened digital frame processing embodiments described herein. | 12-17-2015 |
Patent application number | Description | Published |
20080303089 | INTEGRATED CIRCUIT SYSTEM WITH TRIODE - An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit. | 12-11-2008 |
20090090969 | ELECTRONIC DEVICE AND METHOD OF BIASING - A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge. | 04-09-2009 |
20090253238 | METHOD OF FORMING MULTIPLE FINS FOR A SEMICONDUCTOR DEVICE - A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices. | 10-08-2009 |
20100214008 | SEMICONDUCTOR DEVICE WITH TRANSISTOR-BASED FUSES AND RELATED PROGRAMMING METHOD - A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer. | 08-26-2010 |
Patent application number | Description | Published |
20090231935 | MEMORY WITH WRITE PORT CONFIGURED FOR DOUBLE PUMP WRITE - A memory with a write port configured for double-pump writes. The memory includes a first and second memory locations each having one or more bit cells, and one or more bit lines each coupled to corresponding ones of the bit cells. A write port is coupled to each of the bit lines. Selection circuitry, responsive to a first clock edge, latches first data from a first data path through the write port, and responsive to a second clock edge, latches second data from a second data path through the write port. A first pulse is generated during a first phase of the clock signal to cause writing of the first data into the first memory location. A second pulse is generated during a second phase of the clock signal to cause writing of the second data into the second memory location. | 09-17-2009 |
20100332804 | UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPECULATIVE INSTRUCTIONS - Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields. | 12-30-2010 |
20100332806 | DEPENDENCY MATRIX FOR THE DETERMINATION OF LOAD DEPENDENCIES - Systems and methods for identification of dependent instructions on speculative load operations in a processor. A processor allocates entries of a unified pick queue for decoded and renamed instructions. Each entry of a corresponding dependency matrix is configured to store a dependency bit for each other instruction in the pick queue. The processor speculates that loads will hit in the data cache, hit in the TLB and not have a read after write (RAW) hazard. For each unresolved load, the pick queue tracks dependent instructions via dependency vectors based upon the dependency matrix. If a load speculation is found to be incorrect, dependent instructions in the pick queue are reset to allow for subsequent picking, and dependent instructions in flight are canceled. On completion of a load miss, dependent operations are re-issued. On resolution of a TLB miss or RAW hazard, the original load is replayed and dependent operations are issued again from the pick queue. | 12-30-2010 |
20110078414 | MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSORS EMPLOYING REGISTER WINDOWS - A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output. | 03-31-2011 |
Patent application number | Description | Published |
20090242854 | ADDITIVES AND MODIFIERS FOR SOLVENT- AND WATER-BASED METALLIC CONDUCTIVE INKS - A conductive ink includes metallic nanoparticles, a polymeric dispersant, and a solvent. The polymeric dispersant may be ionic, non-ionic, or any combination of ionic and non-ionic polymeric dispersants. The solvent may include water, an organic solvent, or any combination thereof. The conductive ink may include a stabilizing agent, an adhesion promoter, a surface tension modifier, a defoaming agent, a leveling additive, a rheology modifier, a wetting agent, an ionic strength modifier, or any combination thereof. | 10-01-2009 |
20120142140 | NANOPARTICLE INKS FOR SOLAR CELLS - In a process for producing a solar cell, a sintering process performed on a nickel nanoparticle ink forms nickel silicide to create good adhesion and a low electrical ohmic contact to a silicon layer underneath, and allows for a subsequently electroplated metal layer to reduce electrode resistances. The printed nickel nanoparticles react with the silicon nitride of the antireflective layer to form conductive nickel silicide. | 06-07-2012 |
20150040388 | Application of Dielectric Layer and Circuit Traces on Heat Sink - A dielectric layer is directly applied onto the surface of a heat sink part. For example, the composition for making the dielectric layer may be made into a paste or ink and then printed as a paste or ink, or applied with some other equivalent method, such as a lamination technique. The electrical circuit traces are then printed in a similar fashion onto the dielectric layer in the required pattern for whatever circuitry is to be applied. That circuitry (e.g., circuit elements) is then attached to the electrical traces as needed for the particular application. | 02-12-2015 |
20150184956 | PORE SEALING PASTES FOR POROUS MATERIALS - Embodiments of the present invention disclosed herein use innovative pastes to fill surface pores (cavities) and flatten (planarize) surfaces of porous materials. A method for making a heat transfer apparatus comprises making a paste comprising particles of a first heat transfer material, a vehicle, and a binder, filling cavities on an external surface of a second heat transfer material with the paste, and drying the paste filled in the cavities so that an external, surface of the dried paste in a cavity is substantially planar with the external surface of the second heat transfer material. | 07-02-2015 |
20150201504 | COPPER PARTICLE COMPOSITION - Conductive patterns are formed using formulations containing metallic particles, which may be copper. These metallic particles may be coated with a binder material that improves adhesion during photosintering of the formulations. The binder contains chemistry suitable for it to be removed from the particles in a separate process such as drying or thermal sintering. The coating is a non-volatile organic compound attached to the metallic particles with a minimum thickness oxide coating. The organic coating improves a coefficient of thermal expansion value match between the metallic particles and the substrate, which may be polymeric. | 07-16-2015 |
Patent application number | Description | Published |
20100203340 | PROTECTIVE CARBON COATINGS - Disclosed is a method for forming a protective coating comprising contacting a carbon material with a metal surface, heating the carbon material and metal to allow at least a portion of the carbon material to dissolve in the metal, diffuse across a portion of the metal surface, or a combination thereof, and then cooling the metal and carbon material to form a metal having a protecting carbon coating disposed on a surface thereof, wherein the protective coating comprises graphene, multi-layer graphene, or a combination thereof. Also disclosed are a method for inhibiting corrosion comprising forming a layer of graphene on at least a portion of a metal surface; a metal having a surface, wherein at least a portion of the surface comprises a protective carbon coating comprising graphene, multi-layer graphene, or a combination thereof; and a passivation coating comprising a graphene, multi-layer graphene, or a combination thereof. | 08-12-2010 |
20110091647 | GRAPHENE SYNTHESIS BY CHEMICAL VAPOR DEPOSITION - Processes for synthesizing graphene films. Graphene films may be synthesized by heating a metal or a dielectric on a substrate to a temperature between 400° C. and 1,400° C. The metal or dielectric is exposed to an organic compound thereby growing graphene from the organic compound on the metal or dielectric. The metal or dielectric is later cooled to room temperature. As a result of the above process, standalone graphene films may be synthesized with properties equivalent to exfoliated graphene from natural graphite that is scalable to size far greater than that available on silicon carbide, single crystal silicon substrates or from natural graphite. | 04-21-2011 |
Patent application number | Description | Published |
20080206559 | LUBRICANT ENHANCED NANOCOMPOSITES - Strings configured for use in sports racquets and musical instruments are fabricated as a plastic core wrapped with one or more filaments of plastic. The strings are coated with a material composite that includes rigid nanoparticles, and lubricated nylon. The rigid nanoparticles may include clay or carbon nanotubes. The strings are coated with the material composite using various processes that result in a coating thickness of between 0.1 and 200 μm. The material composite may further include impact modifiers. The strings experience extended life due to reduced frictional wear and improved mechanical properties. | 08-28-2008 |
20080286488 | METALLIC INK - Forming a conductive film comprising depositing a non-conductive film on a surface of a substrate, wherein the film contains a plurality of copper nanoparticles and exposing at least a portion of the film to light to make the exposed portion conductive. Exposing of the film to light photosinters or fuses the copper nanoparticles. | 11-20-2008 |
20090133474 | METHOD AND APPARATUS FOR SENSING HYDROGEN GAS - A hydrogen sensor and/or switch fabricated from an array of nanowires or a nanoparticle thick film composed of metal or metal alloys. The sensor and/or switch demonstrates a wide operating temperature range and shortened response time due to fabrication materials and methods. The nanowires or nanoparticle thick films demonstrate an increase in conductivity in the presence of hydrogen. | 05-28-2009 |
20090242854 | ADDITIVES AND MODIFIERS FOR SOLVENT- AND WATER-BASED METALLIC CONDUCTIVE INKS - A conductive ink includes metallic nanoparticles, a polymeric dispersant, and a solvent. The polymeric dispersant may be ionic, non-ionic, or any combination of ionic and non-ionic polymeric dispersants. The solvent may include water, an organic solvent, or any combination thereof. The conductive ink may include a stabilizing agent, an adhesion promoter, a surface tension modifier, a defoaming agent, a leveling additive, a rheology modifier, a wetting agent, an ionic strength modifier, or any combination thereof. | 10-01-2009 |
20090274833 | METALLIC INK - A metallic ink including a vehicle, a multiplicity of copper nanoparticles, and an alcohol. The conductive metallic ink may be deposited on a substrate by methods including inkjet printing and draw-down printing. The ink may be pre-cured and cured to form a conductor on the substrate. | 11-05-2009 |
20090311440 | PHOTO-CURING PROCESS FOR METALLIC INKS - A solution of metal ink is mixed and then printed or dispensed onto the substrate using the dispenser. The film then is dried to eliminate water or solvents. In some cases, a thermal curing step can be introduced subsequent to dispensing the film and prior to the photo-curing step. The substrate and deposited film can be cured using an oven or by placing the substrate on the surface of a heater, such as a hot plate. Following the drying and/or thermal curing step, a laser beam or focused light from the light source is directed onto the surface of the film in a process known as direct writing. The light serves to photo-cure the film such that it has low resistivity. | 12-17-2009 |
20110217809 | INKS AND PASTES FOR SOLAR CELL FABRICATON - A silicon solar cell is formed with an N-type silicon layer on a P-type silicon semiconductor substrate. An antireflective and passivation layer is deposited on the N-type silicon layer, and then an aluminum ink composition is printed on the back of the silicon wafer to form the back contact electrode. The back contact electrode is sintered to produce an ohmic contact between the electrode and the P-type silicon layer. The aluminum ink composition may include aluminum powders, a vehicle, an inorganic polymer, and a dispersant. Other electrodes on the solar cell can be produced in a similar manner with the aluminum ink composition. | 09-08-2011 |
20110300305 | MECHANICAL SINTERING OF NANOPARTICLE INKS AND POWDERS - Nanoparticle inks and powders are sintered using an applied mechanical energy, such as uniaxial pressure, hydrostatic pressure, and ultrasonic energy, which may also include applying a sheer force to the inks or powders in order to make the resultant film or line conductive. | 12-08-2011 |
20120128878 | Nano-Filler for Composites - A hybrid carbon nanotube and clay nanofiller is produced by a freeze-drying process performed on clay platelets, and carbon nanotubes grown on the clay platelets using a chemical vapor deposition process. | 05-24-2012 |
20120142140 | NANOPARTICLE INKS FOR SOLAR CELLS - In a process for producing a solar cell, a sintering process performed on a nickel nanoparticle ink forms nickel silicide to create good adhesion and a low electrical ohmic contact to a silicon layer underneath, and allows for a subsequently electroplated metal layer to reduce electrode resistances. The printed nickel nanoparticles react with the silicon nitride of the antireflective layer to form conductive nickel silicide. | 06-07-2012 |
20120288991 | BURNTHROUGH FORMULATIONS - For solar cell fabrication, the addition of precursors to printable media to assist etching through silicon nitride or silicon oxide layer thus affording contact with the substance underneath the nitride or oxide layer. The etching mechanism may be by molten ceramics formed in situ, fluoride-based etching, as well as a combination of the two. | 11-15-2012 |
20130017647 | SURFACE-MODIFIED NANOPARTICLE INK FOR PHOTOVOLTAIC APPLICATIONS - Described herein is a novel material that easily penetrates silicon nitride-based anti-reflective coatings, forming a high quality electrical contact. A method for metallization on a solar cell includes depositing a passivation layer on a silicon substrate of a solar cell, depositing derivatized metal particles onto the passive layer, heating the substrate of the solar cell to migrate surface coatings from the derivatized metal particles onto the passivation layer creating a diffusion Channel through passivation layer to the silicon substrate, and as the metal particles melt due to the heating on the substrate, the melted metal diffuses through the diffusion channel forming a metallic content with the silicon substrate. | 01-17-2013 |
20140335651 | INKS AND PASTES FOR SOLAR CELL FABRICATION - A silicon solar cell is formed with an N-type silicon layer on a P-type silicon semiconductor substrate. An aluminum ink composition is printed on the back of the silicon wafer to form back contact electrodes. The back contact electrodes are sintered to produce an ohmic contact between the electrodes and the silicon layers. The aluminum ink composition may include aluminum powders, a vehicle, an inorganic polymer, and a dispersant. Other electrodes on the solar cell can be produced in a similar manner with the aluminum ink composition. | 11-13-2014 |
20150303323 | Metallization Paste for Solar Cells - A metallization paste or ink for making electrical contacts on solar cells has reduced diffusion in a silicon wafer. The paste or ink is configured for printing on a crystalline silicon substrate of a solar cell, wherein the paste comprises silicon particles, aluminum particles, and a paste vehicle. Alternatively, the paste comprises aluminum-silicon alloy particles. | 10-22-2015 |