Patent application number | Description | Published |
20140020185 | CUSHION FOR PREVENTING PRESSURE SORE - The present invention relates to a cushion for preventing pressure sore. The cushion for preventing pressure sore includes an air cell layer, an air passage layer, a base layer, and a plurality of air ducts. The air cell layer has a plurality of air cells; the air cell layer is divided into at least four air cell zones. Air cells in each air cell zone are in communication with each other, but air cells in any two adjacent air cell zones are not in communication with each other; the air passage layer is under the air cell layer and has a plurality of air passages therein. Each air passage is in connection and communication with at least one of the air cell zones; the air passage layer and the air cell layer are disposed on the base layer; an end of each air duct is in communication with a corresponding air passage, and the other end extends out of the cushion and is provided with a joint; and each air duct has a respective valve. The cushion for preventing pressure sore according to the present invention can intermittently exert pressure over human buttocks, thereby effectively preventing pressure sores. | 01-23-2014 |
20140020186 | PRESSURE-REGULATABLE PRESSURE SORES PREVENTION CUSHION - A pressure-regulatable pressure sores prevention cushion is provided. The cushion comprises an air cell array, having a plurality of air cells and being divided into at least four air cell zones, the air cells in each air cell zone being in communication with each other, but air cells in any two adjacent air cell zones being not in communication with each other; a plurality of air passages, located under the air cell array and each of which being connected to and in communication with at least one of the air cell zones; a base, on which the air cell array having a plurality of air cells and the air passages being disposed; a plurality of air ducts, which are disposed within the base, an end of each air duct being in communication with a corresponding air passage, and the other end extending out of the cushion and being provided with a joint, and each air duct having a respective valve; and an automatic pressure regulator, which is in communication with the joints of the plurality of air ducts and electrically connected to the respective valve of each duct to enable the automatic pressure regulator to inflate or deflate each air duct. | 01-23-2014 |
20140217503 | SILICON-ON-INSULATOR RADIO-FREQUENCY DEVICE AND METHOD OF FORMING THE SAME - A silicon-on-insulator (SOI) radio-frequency (RF) device is disclosed, the SOI RF device includes: a silicon substrate; a buried oxide layer formed on the silicon substrate; a device layer formed on the buried oxide layer, the device layer including an RF device; a first dielectric layer covering the device layer; a deep trench structure extending through, from the top downward, the first dielectric layer, the silicon device layer and the buried oxide layer to an interface between the buried oxide layer and the silicon substrate; and a second dielectric layer covering both of the first dielectric layer and the deep trench structure. The SOI RF device is capable of improving signal transmission characteristics and preventing signal distortion, and can be easily manufactured with lower cost in less critical process conditions. A method of forming such an SOI RF device is also disclosed. | 08-07-2014 |
Patent application number | Description | Published |
20140185741 | Multi-energy CT imaging system and Imaging Method - The present invention relates to a Computed Tomography (CT) imaging system, in particular to a multi-energy CT imaging system and imaging method. | 07-03-2014 |
20140369458 | CT IMAGING METHODS AND SYSTEMS - Disclosed is a CT imaging method and system. The method includes: CT scanning an object with a dual-energy CT system to obtain a first complete set of projection data in a first scan mode, and to obtain a second incomplete set of projection data in a second scan mode; reconstructing a first attenuation coefficient image of the object from the first set of projection data, and extracting, from the first attenuation coefficient image, prior structure information of the object indicating edge intensity; and reconstructing a second attenuation coefficient image of the object from the second incomplete set of projection data using the extracted prior structure information as a constraint. With the method using the prior structure information of the imaged object as a constraint in reconstruction, it is possible to dramatically reduce an amount of data required for reconstruction, and achieve satisfactory effects even with ill-conditioned problems of limited-angle and inner reconstruction. | 12-18-2014 |
20150030225 | X-RAY DUAL-ENERGY CT RECONSTRUCTION METHOD - The present disclosure relates to a self-prior information based X-ray dual-energy CT reconstruction method, which can utilize information inherent in data to provide a prior model, thereby obtaining a reconstructed image with a high quality. The X-ray dual-energy CT reconstruction method according to the present disclosure comprises: (a) rating an energy spectrum and establishing a dual-energy lookup table; (b) collecting high-energy data p | 01-29-2015 |
20150185355 | CT SYSTEMS AND METHODS THEREOF - A CT system and method thereof are discloses. The system includes: a conveyor mechanism; a first scanning stage configured to scan the object and generate a first digital signal; a second scanning stage spaced from the first scanning stage at a preset distance in a direction of the object's movement; a processing device configured to reconstruct a CT image of the object at a first image quality based on the first digital signal, and analyze the CT image; and a control device configured to adjust a scanning parameter of the second scanning stage based on an analysis result of the processing device to cause the second scanning stage to output a second digital signal. The processing device reconstructs a CT image of the object at a second image quality higher than the first image quality at least based on the second digital signal. The system takes full advantage of the distributed ray sources which replace the normal slip ring technology. | 07-02-2015 |
20150185357 | MULTI-SPECTRAL STATIC CT APPARATUSES - Multi-spectral static CT apparatuses are disclosed. The apparatus includes a ray source in a form of multiple distributed spots, multiple columns of detectors, a data acquisition device, an article carrying and control device, and a multi-spectral projection data processing device. An object of the present disclosure is to combine static CT scanning technology with multi-spectral analysis technology. It has an advantage of a static CT system, such as high scanning speed, simple mechanic structure, and/or cost reduction due to omission of slip ring. It also can perform identification of material in an article, and can be widely applied in occasions such as safety inspection, and smuggling suppression at customs. | 07-02-2015 |
20150332486 | Spiral CT Systems and Reconstruction Methods - The present disclosure discloses a spiral CT system and a reconstruction method thereof. In some embodiments, it is proposed that data missing due to a large pitch is compensated by weighting the complementary projection data of the projection data obtained using the spiral CT system. After the data is complemented, the projection data is rebinned as cone parallel beam data, cone-angle cosine weighting and one-dimensional filtering are implemented on the rebinned data, and parallel beam back projection is finally implemented on the filtered data, to obtain the reconstructed images. In some embodiments, with the above method, the speed of the belt can be increased by more than one time in a case that the existing area of the detectors and the existing speed of the slip ring are unchanged, thereby improving the pass rate of the luggage and maintaining the quality of the reconstructed images unchanged. | 11-19-2015 |
20150332498 | IMAGE DISPLAY METHODS - The present disclosure discloses an image display method in a CT system. The method comprises: implementing CT scanning on an inspected object, to obtain CT projection data; organizing the CT projection data according to a predetermined interval; extracting basic data from the organized CT projection data by using a fixed angle as a start angle and using 360 degrees as an interval; forming a DR image based on the extracted basic data; reconstructing a three-dimensional image of the inspected object from the CT projection data; and displaying the DR image and the reconstructed three-dimensional image on a screen at the same time. In the solution, the CT data is processed to obtain DR data. After the DR data is obtained, a DR image is obtained directly using a DR data processing algorithm. This enables an image recognizer to more accurately and more rapidly inspect goods carried by a passenger using the existing experience in image recognition of the DR image. | 11-19-2015 |
20150356755 | CT IMAGING SYSTEMS AND METHODS THEREOF - CT imaging systems and methods thereof are disclosed. A common CT scanning is performed on an object to obtain a common CT imaging. An area of interest is determined from the image. A CT scanning is performed on the area of interest under a plurality of energy windows by a photon counter detector. A high resolution image of the area of interest is reconstructed. The discrimination of energy spectrum is higher and the result so obtained is more stable by using a photon counter detector to collect photon count projection data of a plurality of energy windows and thus it may be decomposed into a plurality of basis functions. | 12-10-2015 |
Patent application number | Description | Published |
20090091416 | Wirelessly Powered Secondary Electrical Distribution Equipment - A wireless secondary assembly is disclosed for use in an electrical distribution network. The secondary assembly may include a wireless source electrically connected to a first electric cable and adapted to emit an electromagnetic power signal. A wireless receiver is electrically connected to a secondary device and adapted to receive the electromagnetic power signal and convert the electromagnetic power signal to electricity to power to secondary device. | 04-09-2009 |
20090299542 | Collaborative Defense of Energy Distribution Protection and Control Devices - A method is disclosed for preventing malicious settings changes to IEDs in a power transmission and distribution network. Attempted changes to the protection settings of an IED is detected and transmitted to one or more neighboring IEDs. The neighboring IEDs check for consistency of the new settings and return conformance or nonconformance signals. If a nonconformance signal is received, the attempted setting change is not allowed. | 12-03-2009 |
20100201338 | HYBRID DISTRIBUTION TRANSFORMER WITH AC & DC POWER CAPABILITIES - A hybrid transformer is provided that includes an electromagnetic transformer and an AC-AC converter with a DC bridge. The AC-AC converter is operable to keep the input voltage and current of the hybrid transformer substantially in phase and to reduce fluctuation in the output voltage of the hybrid transformer in the event of an increase or decrease in the input voltage. | 08-12-2010 |
20100220499 | HYBRID DISTRIBUTION TRANSFORMER WITH AN INTEGRATED VOLTAGE SOURCE CONVERTER - A hybrid distribution transformer is provided that includes an electromagnetic transformer and a voltage source converter that is operable to reduce fluctuation in the output voltage of the hybrid distribution transformer in the event of an increase or decrease in the input voltage. | 09-02-2010 |
20120113555 | FAULT INTERRUPTING DEVICES AND CONTROL METHODS THEREFOR - Fault interrupting devices and methods for controlling the same are disclosed. The fault interrupting devices may include a switch on an electrical power line and a controller configured to operate the switch. The methods for controlling fault interrupting devices may include gathering data, determining from the data that a fault has occurred, opening the fault interrupting device to interrupt the fault, analyzing the data, and determining whether the fault interrupting device can be reclosed based at least partially on the analysis of the data. | 05-10-2012 |
Patent application number | Description | Published |
20120178230 | METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR - A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication. | 07-12-2012 |
20120256252 | COMPATIBLE VERTICAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND MANUFACTURE METHOD THEREOF - A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source. | 10-11-2012 |
20130102139 | METHOD FOR MANUFACTURING DOUBLE-GATE STRUCTURES - A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region. | 04-25-2013 |
20130109146 | METHOD FOR FABRICATING SMALL-SCALE MOS DEVICE | 05-02-2013 |
20130113052 | METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region. | 05-09-2013 |
Patent application number | Description | Published |
20140103897 | GLITCH SUPPRESSION IN DC-TO-DC POWER CONVERSION - Exemplary embodiments are directed to devices and method for operating a charge pump. A method may include activating a first switch coupled between a capacitor and a ground voltage over a first period of a charging phase. The first period may coincide with a non-overlapping time between the charging phase and an output phase. The method may also include activating a second switch coupled between the capacitor and an input voltage over a second period of the charging phase, wherein the first period begins prior to the second period. Further, the method may include deactivating the second switch over a third period of the charging phase and deactivating the first switch over a fourth period of the charging phase, wherein the third period begins prior to the fourth period. | 04-17-2014 |
20140253180 | CHARGE PUMP POWER SAVINGS - Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency. | 09-11-2014 |
20150304137 | TRANSMISSION GATE FOR BIAS VOLTAGE GENERATION - An apparatus includes a transmission gate configured to generate a signal based on a first differential input signal and a second differential input signal. The apparatus further includes biasing circuitry responsive to the transmission gate and configured to output a bias voltage based on the signal. | 10-22-2015 |
20150349710 | RC OSCILLATOR BASED ON DELAY-FREE COMPARATOR - Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor. | 12-03-2015 |
Patent application number | Description | Published |
20140071692 | Lens, LED Module and Illumination System having Same - An illumination system includes at least an LED module, and at least an illuminated area. The LED module includes an LED, and a lens mounted in light path of the LED. The lens includes a light source recess, a first light emitting surface, a critical reflecting surface, and a second light emitting surface intersecting with the first light emitting surface and being on same side with the first light emitting surface. The first light emitting surface can receive more light quantity than the second light emitting surface. Although the light emitted from the first light emitting surface may have greater attenuation than the light emitted from the second light emitting surface, light emitted from the first light emitting surface can make up the intensity losses of attenuation as the first light emitting surface receives more light quantity than the second light emitting surface. As a result, the illumination system | 03-13-2014 |
20140071693 | Lens, LED Module and Illumination System having Same - An illumination system includes an LED module and an illuminated area. The LED module includes an LED, and a lens mounted in light path of the LED. The lens includes a light source recess, a first light emitting surface, a critical reflecting surface, and a second light emitting surface intersecting with the first light emitting surface and being on same side with the first light emitting surface. The first light emitting surface can receive more light quantity than the second light emitting surface. Although the light emitted from the first light emitting surface may have greater attenuation than the light emitted from the second light emitting surface, light emitted from the first light emitting surface can make up the intensity losses of attenuation as the first light emitting surface receives more light quantity than the second light emitting surface. As a result, the illumination system has a uniform illumination pattern. | 03-13-2014 |
20140071694 | Lens, LED Module and Illumination System having Same - An illumination system includes at least an LED module, and at least an illuminated area. The LED module includes an LED, and a lens mounted in light path of the LED. The lens includes a light source recess, a first light emitting surface, a critical reflecting surface, and a second light emitting surface. The first light emitting surface can receive more light quantity than the second light emitting surface. In result, although the light emitted from the first light emitting surface may have greater attenuation than the light emitted from the second light emitting surface, light emitted from the first light emitting surface, which is father to the illuminated are, can make up the intensity losses of attenuation as the first light emitting surface receives more light quantity than the second light emitting surface. As a result, the illumination system has a uniform illumination pattern. | 03-13-2014 |
20140160731 | LED LAMP AND ILLUMINATION AREA HAVING SAME - A freezer lamp includes a strip lamp holder, a light module and a socket. The light module is disposed in the strip lamp holder. The socket is disposed on the end of the strip lamp holder and electrically connected to the light module. The strip lamp holder includes a main lateral surface and a mounting lateral surface. An installation groove is formed in the main lateral surface along length direction thereof. The light module is received into the installation groove. Two clamping grooves are formed in the mounting lateral surface along length direction thereof and are spaced apart from each other. The distance between the two clamping edges is exactly equal to that between the two clamping grooves. The clamping edge is cooperating with the corresponding buckle of clamping groove. | 06-12-2014 |
Patent application number | Description | Published |
20110148655 | USB FLASH DRIVE AND METHOD FOR DETERMINING AVAILABLE STORAGE CAPACITY OF THE USB FLASH DRIVE - A Universal Serial Bus (USB) flash drive includes an USB interface, a control unit, a storage unit, a timer, a logic circuit, and a quartz meter that includes a scale dial and a dial pointer. The control unit calculates a storage capacity difference between a current storage capacity and a previous storage capacity, and calculates a runtime of the dial pointer according to a time calculation algorithm. The control unit generates an enabling signal if the storage capacity difference is not equal to zero, and generates an interrupt signal when the runtime equals the time value. The logic circuit outputs a high voltage to the quartz meter to control the dial pointer to run around the scale dial according to the enabling signal, and outputs a low voltage to the quartz meter to control the dial pointer to stop running around the scale dial according to the interrupt signal. | 06-23-2011 |
20110309947 | LIGHT-EMITTING DIODE CONTROL SYSTEM AND METHOD - A light-emitting diode (LED) control system and method sets a number of virtual LEDs according to a number of error events of a computing device. The system and method further assigns a priority level to each error event and a unique indication status of the error event. If more than one error event occurs to the computing device, each error event is indicated by a virtual LED by a unique indication status, however, only the error event having the highest priority level is synchronously indicated by a virtual LED and the physical LED. | 12-22-2011 |
20120166919 | DATA PROCESSING DEVICE AND METHOD FOR CHECKING PARAMETER VALUES OF THE DATA PROCESSING DEVICE - A data processing device acquires a first parameter value of a hardware component, and calculates a first prediction value of the first parameter using a prediction algorithm. If a difference of the first prediction value and the first parameter falls within a deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the device acquires a second parameter value of the hardware component that follows the first parameter value, and calculates a second prediction value of the second parameter value. If a difference between the second prediction value and the second parameter value falls with a second deviation range, the first parameter value is determined as a real value and is stored. Otherwise, the first parameter value is determined as a false value and is abandoned. | 06-28-2012 |