Patent application number | Description | Published |
20090176707 | HUMAN SIGNAL PEPTIDE-CONTAINING PROTEINS - The invention provides a human signal peptide-containing proteins (SIGP) and polynucleotides which identify and encode SIGP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for treating or preventing disorders associated with expression of SIGP. | 07-09-2009 |
20090274680 | Human Phospholipases - The invention provides human lipid metabolism enzymes (LME) and polynucleotides which identify and encode LME. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of LME. | 11-05-2009 |
20100136564 | STEROID RESPONSIVE NUCLEIC ACID EXPRESSION AND PREDICTION OF DISEASE ACTIVITY - The invention relates to methods useful for diagnosing and monitoring the steroid responsiveness of a subject by detecting expression of steroid modulated genes and for predicting transplant rejection and non-rejection. | 06-03-2010 |
20110053217 | Polynucleotides encoding signal peptide-containing molecules - The invention provides human signal peptide-containing proteins (HSPP) and polynucleotides which identify and encode HSPP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with expression of HSPP. | 03-03-2011 |
20120270809 | HUMAN TRANSMEMBRANE PROTEINS - The invention provides human transmembrane proteins (HTMPN) and polynucleotides which identify and encode HTMPN. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with expression of HTMPN. | 10-25-2012 |
20130244927 | POLYNUCLEOTIDES ENCODING SIGNAL PEPTIDE-CONTAINING MOLECULES - The invention provides human signal peptide-containing proteins (HSPP) and polynucleotides which identify and encode HSPP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with expression of HSPP. | 09-19-2013 |
Patent application number | Description | Published |
20140155288 | METHODS FOR DIAGNOSING CANCER - The invention provides cDNAs which encodes a signal peptide-containing proteins. It also provides for the use of a cDNA, protein, and antibody in the diagnosis, prognosis, treatment and evaluation of therapies for cancer. The invention further provides vectors and host cells for the production of the protein and transgenic model systems. | 06-05-2014 |
20140242086 | POLYNUCLEOTIDES ENCODING SIGNAL PEPTIDE-CONTAINING MOLECULES - The invention provides human signal peptide-containing proteins (HSPP) and polynucleotides which identify and encode HSPP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with expression of HSPP. | 08-28-2014 |
20150017173 | ANTIBODIES TO HUMAN TRANSMEMBRANE PROTEINS - The invention provides human transmembrane proteins (HTMPN) and polynucleotides which identify and encode HTMPN. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with expression of HTMPN. | 01-15-2015 |
20150291701 | METHODS FOR TREATING DISORDERS ASSOCIATED WITH HUMAN SIGNAL PEPTIDE-CONTAINING MOLECULES - The invention provides human signal peptide-containing proteins (HSPP) and polynucleotides which identify and encode HSPP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with expression of HSPP. | 10-15-2015 |
Patent application number | Description | Published |
20080241158 | Human taste-specific receptor TIR3 - The invention provides human G-protein coupled receptors (GCREC) and polynucleotides which identify and encode GCREC. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of GCREC. | 10-02-2008 |
20090298060 | METHODS FOR DIAGNOSING AND MONITORING THE STATUS OF SYSTEMIC LUPUS ERYTHEMATOSUS - The invention presents a method of diagnosing or monitoring the status of systemic lupus erythematosus (SLE) in a subject or patient comprising detecting the expression of all genes of a diagnostic set in the subject or patient wherein the diagnostic set comprises two or more genes having expression correlated with the classification or status of SLE; and diagnosing or monitoring the status of SLE in the subject or patient by applying at least one statistical method to the expression of the genes of the diagnostic set. | 12-03-2009 |
20100092989 | GENES USEFUL FOR DIAGNOSING AND MONITORING INFLAMMATION RELATED DISORDERS - Described herein is a system for monitoring gene expression for diagnosing and monitoring inflammation disorders, and for monitoring gene expression in inflammation disorders in response to a particular drug treatment regimen. This system for detecting nucleic acid expression in a body fluid uses an isolated polynucleotide to detect expression of a nucleic acid comprising a nucleotide sequence selected from the group consisting of SEQ ID NO: 5; SEQ ID NO:11; SEQ ID NO:17; and SEQ ID NO: 23. These nucleic acids are differentially expressed in body fluid in an individual with a disease criterion for a disease as listed in Table 1 as compared to an individual without the disease criterion. | 04-15-2010 |
20100099617 | Secreted proteins - The invention provides human secreted proteins (SECP) and polynucleotides which identify and encode SECP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of SECP. | 04-22-2010 |
20130190250 | Polynucleotides Encoding Human Signal Peptide-Containing Proteins - The invention provides a human signal peptide-containing proteins (SIGP) and polynucleotides which identify and encode SIGP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for treating or preventing disorders associated with expression of SIGP. | 07-25-2013 |
20130243781 | SIGNAL PEPTIDE-CONTAINING PROTEINS - The invention provides cDNAs which encodes a signal peptide-containing proteins. It also provides for the use of a cDNA, protein, and antibody in the diagnosis, prognosis, treatment and evaluation of therapies for cancer. The invention further provides vectors and host cells for the production of the protein and transgenic model systems. | 09-19-2013 |
20140056906 | SECRETED PROTEINS - The invention provides human secreted proteins (SECP) and polynucleotides which identify and encode SECP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of SECP. | 02-27-2014 |
Patent application number | Description | Published |
20090271305 | PAYMENT PORTFOLIO OPTIMIZATION - A method and system of payment portfolio optimization that retrieves information associated with a plurality of consumers in a consumer portfolio, separates by a diagnostics module on a computer the plurality of consumers into consumer segments based on segment definitions, analyzes by a diagnostics module on the computer the consumer segments using the retrieved information based on a plurality of performance metrics, and identifies revenue opportunities associated with the plurality of consumer segments based on the results from the analysis. | 10-29-2009 |
20090271327 | PAYMENT PORTFOLIO OPTIMIZATION - A method and system of payment portfolio optimization that retrieves a plurality of consumer segments of a consumer portfolio from a diagnostics module where the consumer segments have potentially profitable opportunities. The method and system also develop a propensity model on a computer based on at least one performance metric, determine a likelihood from the propensity model that consumers in each of the plurality of consumer segments will perform favorably. The method and system also selects a set of consumer segments from the plurality of consumer segments based on the determined likelihood and designs a plurality of marketing treatments for the selected set of consumer segments. | 10-29-2009 |
20090327107 | CONSUMER SPENDING THRESHOLD EVALUATION - A method comprising receiving, by a server computer, an authorization request for a transaction conducted with a payment token from a merchant via an open payment processing network. The payment token associated with an account having a no preset spending limit. The method also determines, by the server computer, an exposure limit of the account in real-time based on information obtained by the open payment processing network. The method also determines, by the server computer, whether or not to authorize the transaction based on the determined exposure limit. | 12-31-2009 |
20100198669 | METHOD AND SYSTEM FOR CONDUCTING TRANSACTIONS WITH OLIGOPOLISTIC ENTITIES - A method for conducting a business transaction using a payment processing network is disclosed. The method includes sending an authorization request message including an authorization request to an issuer, where the authorization request message originates from a business consumer purchasing goods or services from an oligopolistic business entity. The issuer sends an authorization response message indicating that the authorization request is approved or not approved. Economic incentives associated with the business transaction is provided to the oligopolistic business entity or the business consumer for conducting the business transaction, wherein the incentive would not be available in a transaction between a non-oligopolistic business entity and the business consumer. A method for encouraging use of electronic payment methods is also disclosed, wherein an oligopolistic entity and a group of business consumers in an industry vertical are identified based on sales information, and an economic incentive is provided to the oligopolistic business entity after it agrees to accept electronic payment transactions for conducting business with the group of business consumers. | 08-05-2010 |
20100268588 | LOYALTY REWARDS OPTIMIZATION BILL PAYABLES AND RECEIVABLES SERVICE - For several accounts receivable, a reward account is determined as the account that receives the largest deposit to the loyalty reward balance thereof by a payment of the account receivable. For each reward account, a deficient reward account is found if the currency balance for the reward account is not sufficient for the payment of the account payable. For each deficiency reward account, if identified accounts receivables can be deposited such that the currency balance thereof will be sufficient to pay the account payable, then payments are made of: (i) the identified accounts receivables as corresponding deposits to the currency balance of the deficiency reward account such that the currency balance thereof is sufficient for the payment of the account payable; and (ii) the account payable by a withdrawal from the currency balance of the deficiency reward account. | 10-21-2010 |
20110022514 | Loyalty Rewards Optimization Bill Payables and Receivables Service - For several accounts receivable, a reward account is determined as the account that receives the largest deposit to the loyalty reward balance thereof by a payment of the account receivable. For each reward account, a deficient reward account is found if the currency balance for the reward account is not sufficient for the payment of the account payable. For each deficiency reward account, if identified accounts receivables can be deposited such that the currency balance thereof will be sufficient to pay the account payable, then payments are made of: (i) the identified accounts receivables as corresponding deposits to the currency balance of the deficiency reward account such that the currency balance thereof is sufficient for the payment of the account payable; and (ii) the account payable by a withdrawal from the currency balance of the deficiency reward account. | 01-27-2011 |
20130191192 | Method and System for Conducting Transactions With Oliogopolistic Entities - A method for conducting a business transaction using a payment processing network is disclosed. The method includes sending an authorization request message including an authorization request to an issuer, where the authorization request message originates from a business consumer purchasing goods or services from an oligopolistic business entity. The issuer sends an authorization response message indicating that the authorization request is approved or not approved. Economic incentives associated with the business transaction is provided to the oligopolistic business entity or the business consumer for conducting the business transaction, wherein the incentive would not be available in a transaction between a non-oligopolistic business entity and the business consumer. A method for encouraging use of electronic payment methods is also disclosed, wherein an oligopolistic entity and a group of business consumers in an industry vertical are identified based on sales information, and an economic incentive is provided to the oligopolistic business entity after it agrees to accept electronic payment transactions for conducting business with the group of business consumers. | 07-25-2013 |
20140304057 | LOYALTY REWARDS OPTIMIZATION BILL PAYABLES AND RECEIVABLES SERVICE - For several accounts receivable, a reward account is determined as the account that receives the largest deposit to the loyalty reward balance thereof by a payment of the account receivable. For each reward account, a deficient reward account is found if the currency balance for the reward account is not sufficient for the payment of the account payable. For each deficiency reward account, if identified accounts receivables can be deposited such that the currency balance thereof will be sufficient to pay the account payable, then payments are made of: (i) the identified accounts receivables as corresponding deposits to the currency balance of the deficiency reward account such that the currency balance thereof is sufficient for the payment of the account payable; and (ii) the account payable by a withdrawal from the currency balance of the deficiency reward account. | 10-09-2014 |
Patent application number | Description | Published |
20090134041 | Compact electric appliance providing hydrogen injection for improved performance of internal combustion engines - Devices, systems and methods for improved electrical appliances which allow for efficient and safe production of hydrogen and oxygen gas for internal combustion engines and the like are disclosed. An appliance for providing gas for combustion may comprise a water inlet, a power source, and an electrolyzer with at least one electrolysis transistor generating hydrogen and oxygen. The appliance may also comprise a gas handling unit for collecting the output of the electrolyzer and transporting it to an engine. | 05-28-2009 |
20090145771 | Compact electric appliance for providing gas for combustion - Devices, systems and methods for improved electrical appliances which allow for efficient and safe production of hydrogen and oxygen gas for a flame are disclosed. An appliance for providing gas for combustion may comprise a water inlet, a power source, and an electrolyzer with at least one electrolysis transistor generating hydrogen and oxygen. The appliance may also comprise a gas handling unit for collecting the output of the electrolyzer and transporting it to a burner, and an output interface. | 06-11-2009 |
20130140189 | Compact electric appliance for providing gas for combustion - Devices, systems and methods for improved electrical appliances which allow for efficient and safe production of hydrogen and oxygen gas for a flame are disclosed. An appliance for providing gas for combustion may comprise a water inlet, a power source, and an electrolyzer with at least one electrolysis transistor generating hydrogen and oxygen. The appliance may also comprise a gas handling unit for collecting the output of the electrolyzer and transporting it to a burner, and an output interface. | 06-06-2013 |
Patent application number | Description | Published |
20110140172 | REVERSE SIDE ENGINEERED III-NITRIDE DEVICES - Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a | 06-16-2011 |
20130088280 | HIGH POWER SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INCREASED RELIABILITY - An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor. | 04-11-2013 |
20130210220 | METHODS OF FORMING REVERSE SIDE ENGINEERED III-NITRIDE DEVICES - Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed. | 08-15-2013 |
20140099757 | III-N Device Structures and Methods - A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive. | 04-10-2014 |
20140264431 | ENHANCEMENT-MODE III-NITRIDE DEVICES - A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact. | 09-18-2014 |
20140377930 | METHOD OF FORMING ELECTRONIC COMPONENTS WITH INCREASED RELIABILITY - An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor. | 12-25-2014 |
20150021552 | III-NITRIDE TRANSISTOR INCLUDING A P-TYPE DEPLETING LAYER - A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages. | 01-22-2015 |
20150041861 | III-N DEVICE STRUCTURES AND METHODS - A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive. | 02-12-2015 |
20150263112 | ENHANCEMENT-MODE III-NITRIDE DEVICES - A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact. | 09-17-2015 |
Patent application number | Description | Published |
20110147874 | PHOTODIODE ISOLATION IN A PHOTONIC INTEGRATED CIRCUIT - Consistent with the present disclosure, a current blocking layer is provided between output waveguides carrying light to be sensed by the photodiodes in a balanced photodetector, and the photodiodes themselves. Preferably, the photodiodes are provided above the waveguides and sense light through evanescently coupling with the waveguides. In addition, the current blocking layer may include alternating p and n-type conductivity layers, such that, between adjacent ones of such layers, a reverse biased pn-junction is formed. The pn-junctions, therefore, limit the amount of current flowing from one photodiode of the balanced detector to the other, thereby improving performance. | 06-23-2011 |
20110150384 | OPTICAL INTEGRATED CIRCUIT - Consistent with the present disclosure, a non-adiabatic polarization rotator is provided that can rotate the polarization of an incoming over a relatively short length. Light is supplied to the polarization rotator via a polarizer, which insures that the optical input to the polarization polarization rotator has a desired polarization. Preferably, the polarization rotator has a structure that is readily implemented with semiconductor materials and can be fabricated with known processing techniques. In addition, the polarization rotator and polarizer may include similar materials and/or layers, such that both may be readily integrated on a common substrate, such as an indium phosphide (InP) substrate. | 06-23-2011 |
20120002912 | FABRICATION TOLERANT POLARIZATION CONVERTER - The present invention provides a polarization converter, and a method for fabricating the same. The polarization converter includes a geometric shape which induces rotation of a polarization of an optical signal from a first polarization state to a second polarization state as the optical signal propagates along the polarization converter. The performance of the polarization converter is maintained in light of inconsistencies in fabrication processes resulting in improved manufacturability. | 01-05-2012 |
20140133868 | INTENSITY-BASED MODULATOR - An optical modulator includes a splitter, phase modulators, amplitude modulators, intensity modulators, and a combiner. The splitter is configured to receive light, and split the light into portions of the light. Each of the phase modulators is configured to receive a corresponding one of the portions of the light, and modulate a phase of the portion of the light to provide a phase-modulated signal. Each of the amplitude modulators is configured to receive a corresponding one of the phase-modulated signals, and modulate an amplitude of the phase-modulated signal to provide an amplitude-modulated signal. Each of the intensity modulators is configured to receive a corresponding one of the amplitude-modulated signals, and modulate an intensity of the amplitude-modulated signals to provide an intensity-modulated signal. The combiner is configured to receive the intensity-modulated signals, combine the intensity-modulated signals into a combined signal, and output the combined signal. | 05-15-2014 |
20150318952 | HYBRID OPTICAL TRANSMITTER AND/OR RECEIVER STRUCTURE - A device may include a substrate. The device may include a carrier mounted to the substrate. The device may include a transmitter photonic integrated circuit (PIC) mounted on the carrier. The transmitter PIC may include a plurality of lasers that generate an optical signal when a voltage or current is applied to one of the plurality of lasers. The device may include a first microelectromechanical structure (MEMS) mounted to the substrate. The first MEMS may include a first set of lenses. The device may include a planar lightwave circuit (PLC) mounted to the substrate. The PLC may be optically coupled to the plurality of lasers by the first set of lenses of the first MEMS. The device may include a second MEMS, mounted to the substrate, that may include a second set of lenses, which may be configured to optically couple the PLC to an optical fiber. | 11-05-2015 |
Patent application number | Description | Published |
20120124339 | PROCESSOR CORE SELECTION BASED AT LEAST IN PART UPON AT LEAST ONE INTER-DEPENDENCY - An embodiment may include at least one first process to be executed, at least in part, by circuitry. The at least one first process may select, at least in part, from a plurality of processor cores, one or more processor cores to execute, at least in part, at least one second process. The at least one first process may select, at least in part, the one or more processor cores based at least in part upon whether at least one inter-dependency exists, at least in part, between the at least one second process and at least one third process also to be executed by the one or more processor cores. Many alternatives, variations, and modifications are possible. | 05-17-2012 |
20140052276 | Techniques for Ceiling Space or Floor Space Mountable Network Computing Devices - Examples are disclosed for operating, managing or controlling one or more network computing devices housed in a chassis capable of being mounting in a ceiling space or a floor space for a room. Operating, managing or controlling may include adjusting one or more fans to direct airflow either away or towards the room or powering a light emitting diode array attached with the chassis to provide lighting to the room. Examples are also disclosed for using an aggregator to operate, manage or control an array of network computing devices separately housed in chassis capable of being mounted in a ceiling space or floor space for one or more rooms. | 02-20-2014 |
20140075179 | Techniques for Managing or Controlling Computing Devices - Examples are disclosed for receiving or gathering asset information associated with computing devices housed in respective decentralized locations. The gathered or received asset information may be stored. A portion of the computing devices may be grouped based on the stored asset information to create a virtual rack. An operating parameter of at least some of the computing devices included in the virtual rack may then be managed or controlled. | 03-13-2014 |
20140089603 | Techniques for Managing Power and Performance of Multi-Socket Processors - Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate. | 03-27-2014 |
20150033055 | Techniques for Managing Power and Performance of Multi-Socket Processors - Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate. | 01-29-2015 |