Patent application number | Description | Published |
20090165849 | TRANSPARENT SOLAR CELL MODULE - A transparent solar cell module including a transparent solar cell and an optical filter is provided. The transparent solar cell includes a transparent substrate and a transparent solar cell part located on a first surface of the transparen substrate. The optical filter is located on the transparent solar cell. | 07-02-2009 |
20090277500 | TRANSPARENT SOLAR CELL MODULE - A transparent solar cell module including a transparent solar cell and an optical transparent substrate is provided. The optical transparent substrate includes an optical filter and a first transparent substrate. The transparent solar cell includes a first electrode, a photoelectric conversion layer, a second electrode, and a second transparent substrate in sequence. | 11-12-2009 |
20100126579 | SOLAR CELL HAVING REFLECTIVE STRUCTURE - A solar cell having a reflective structure is provided, which includes a front contact, a P layer, an I layer, an N layer, and a back contact that are stacked together. The solar cell having the reflective structure is characterized in that the N layer is a layer of low refraction index, and a refraction index of the layer of low refraction index is lower than that of the I layer. Furthermore, the N layer may be a multi-layer structure consisting of several films in which films with low refraction indexes and films with high refraction indexes are stacked alternately. The film in contact with the I layer in the multi-layer structure is a film of low refraction index. A refraction index of the film of low refraction index is lower than that of the I layer. | 05-27-2010 |
20100154881 | TRANSPARENT SOLAR CELL MODULE AND METHOD OF FABRICATING THE SAME - A transparent solar cell module is provided. The transparent solar cell module includes a transparent substrate, a first transparent electrode on the transparent substrate, a p-type layer on the first transparent electrode, an intrinsic layer on the p-type layer, an n-type stacked layer on the intrinsic layer, and a second transparent electrode on the n-type stacked layer. The n-type stacked layer includes at least two n-type material layers with different refractive indexes. | 06-24-2010 |
Patent application number | Description | Published |
20100237367 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes a carrier, an LED chip, an encapsulant, a plurality of phosphor particles, and a plurality of anti-humidity particles. The LED chip is disposed on and electrically connected to the carrier. The encapsulant encapsulates the LED chip. The phosphor particles and the anti-humidity particles are distributed within the encapsulant. A first light emitted from the LED chip excites the phosphor particles to emit a second light. Some of the anti-humidity particles are adhered onto a surface of the phosphor particles, while the other anti-humidity particles are not adhered onto the surface of the phosphor particles. The anti-humidity particles absorb H | 09-23-2010 |
20100258818 | LIGHT EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of an LED chip. First, a device layer is formed on a growth substrate, wherein the device layer has a first surface connected to the growth substrate and a second surface. Next, a plurality of first trenches are formed on the second surface of the device layer. Then, a protection layer is formed on the side walls of the first trenches. After that, the second surface is bonded with a supporting substrate and the device layer is then separated from the growth substrate. Further, a plurality of second trenches corresponding to the first trenches are formed in the device layer to form a plurality of LEDs, wherein the second trenches extend from the first surface to the bottom portions of the first trenches. Furthermore, a plurality of electrodes are formed on the first surface of the device layer. | 10-14-2010 |
20100258827 | LIGHT-EMITTING DIODE PACKAGE AND WAFER-LEVEL PACKAGING PROCESS OF LIGHT-EMITTING DIODE - A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug. | 10-14-2010 |
20100261299 | PACKAGING PROCESS OF LIGHT EMITTING DIODE - A packaging process of a light emitting diode (LED) is provided. First, an LED chip is bonded with a carrier to electrically connect to each other. After that, the carrier is heated to raise the temperature thereof. Next, an encapsulant is formed on the heated carrier by a dispensing process to encapsulate the LED chip, wherein the viscosity of the encapsulant before contacting the carrier is lower than that of the encapsulant after contacting the carrier. Thereafter, the encapsulant is cured. | 10-14-2010 |
20110057207 | WHITE-LIGHT EMITTING DEVICE - An white-light emitting device including a carrier, light emitting diode (LED) chips, and a wavelength converting material is provided. The LED chips are disposed on and electrically connected to the carrier. An equivalent wavelength of the first light emitted from the LED chips and divided into groups is λ. A variation of peak wavelengths of the LED chips in one group is smaller than 5 nm. λ meets an equation: | 03-10-2011 |
20110312113 | LIGHT-EMITTING DIODE STRUCTURE WITH ELECTRODE PADS OF SIMILAR SURFACE ROUGHNESS AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode (LED) structure and a method for manufacturing the LED structure are disclosed for promoting the recognition rate of LED chips, wherein a roughness degree of the surface under a first electrode pad of a first conductivity type is made similar to that of the surface under a second electrode pad of a second conductivity type, so that the luster shown from the first electrode pad can be similar to that from the second electrode pad, thus resolving the poor recognition problem of wire-bonding machines caused by different lusters from the first and second electrode pads. | 12-22-2011 |
20120164768 | Light-Emitting Diode Package and Wafer-Level Packaging Process of Light-Emitting Diode - A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug. | 06-28-2012 |
20120168768 | SEMICONDUCTOR STRUCTURES AND METHOD FOR FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes: a substrate; one or more semiconductor device layers formed on the substrate; and one or more lattice breaking areas formed on the surface of the substrate between the semiconductor device layers. The invention also provides a method for fabricating a semiconductor structure. | 07-05-2012 |
20140231858 | LED Sub-Mount and Method for Manufacturing Light Emitting Device Using the Sub-Mount - A LED sub-mount includes a substrate body and a plurality of first electrical-conductive layers. The substrate body has a first surface. The first electrical-conductive layers are positioned on the first surface of the substrate body, wherein the first surface between every adjacent two of the first electrical-conductive layers has an adhesive-filling groove. | 08-21-2014 |
20150034959 | PATTERNED SUBSTRATE AND LIGHT EMITTING DIODE STRUCTURE HAVING THE SAME - A light emitting diode structure includes a patterned substrate, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer. Plural protruding portions are formed on a surface of the substrate. A horizontal projection of each of the protruding portions on the surface of the substrate has a projection width W | 02-05-2015 |
20150077996 | HEAT SINK FOR ELECTRICAL ELEMENTS AND LIGHT-EMITTING DEVICE CONTAINING THEREOF - The disclosure provides a heat sink for electrical elements and a light-emitting device containing thereof. The heat sink includes a radiating substrate and at least one hollow radiating channel. In which, the hollow radiating channel is horizontally embedded in the radiating substrate, and has two openings disposed on the same site or the opposite sites of the radiating substrate, so that gas may flow in the hollow radiating channel and remove heat of the radiating substrate. And a light-emitting device containing the heat sink is also provided. | 03-19-2015 |
Patent application number | Description | Published |
20130106711 | HIERARCHICAL SENSING METHOD | 05-02-2013 |
20130135216 | TOUCH COORDINATE CALCULATION METHOD FOR TOUCH PANEL - A method for calculating a touch coordinate on a touch panel is provided, the touch panel having a plurality of points, said method comprising: determining a group of candidate points when a touch occurs on the touch panel, each candidate point having one sensing value; assigning weights to the sensing values of the respective candidate points to obtain weighted sensing values; and calculating a coordinate by utilizing the weighted sensing values and positions of the respective candidate points. By using said method, the calculation result of the touch coordinate will be more stable. | 05-30-2013 |
20130265271 | METHOD OF REDUCING COMPUTATION OF PALM REJECTION BY PROJECTING TOUCH DATA - A method of reducing computation of palm rejection by projecting touch data is disclosed, targeting the handheld devices. The method targets first at obtaining a difference array, followed by extracting maximum values of rows and columns of the difference array to obtain a row projection list and a column projection list respectively. By repeated implementing of mutual capacitance detection, ghost palm blocks can be wiped out from the multiple palm blocks. Once integrating with a local spatial boundary detection algorithm, the sensed signals of intended input located within a rectangular palm block yet beyond a real palm block are consequently detected. The computational algorithm of the palm rejection of this invention is successfully built into the touch panel controller due to its substantially reduced computation. | 10-10-2013 |
20130278543 | METHOD OF REDUCING COMPUTATION OF WATER TOLERANCE BY PROJECTING TOUCH DATA - A method of reducing computation of water tolerance by projecting touch data is disclosed, targeting the handheld devices. The method targets first at obtaining a difference array, followed by extracting minimum values of rows and columns of the difference array to obtain a row projection list and a column projection list respectively. By repeated implementing of mutual capacitance detection, ghost water blocks can be wiped out from the multiple water blocks. Once integrating with a local spatial boundary detection algorithm, the sensed signals of intended input located within a rectangular water block yet beyond a real water block are consequently detected. The computational algorithm of the water tolerance of this invention is successfully built into the touch panel controller due to its substantially reduced computation. | 10-24-2013 |
Patent application number | Description | Published |
20100268800 | METHOD AND APPARATUS FOR CONFIGURING NETWORK-ATTACHED STORAGE - A method for configuring a network-attached storage (NAS) includes: coupling the network-attached storage to a user-end personal computer (PC) via an external bus which supports a plug & play function; and utilizing the user-end PC to configure a network interface of the NAS via the external bus. A network-attached storage (NAS) includes a network interface, a bus interface, and processor. The network interface is for connecting with a network. The bus interface is for connecting with an external bus which supports a plug & play function and for receiving network interface setting parameters outputted by a user-end PC via the external bus. The processor is coupled between the network interface and the bus interface, and implemented for configuring the network interface according to the network interface setting parameters received by the bus interface. | 10-21-2010 |
20100332777 | DATA BACKUP APPARATUS AND DATA BACKUP METHOD - A data backup apparatus includes a host interface, a first storage medium interface, a second storage medium interface and a controller. The host interface is utilized to be electrically connected with a host, the first storage medium interface is utilized to be electrically connected with a first storage medium, and the second storage medium interface is utilized to be electrically connected with a second storage medium. The controller is coupled to the host interface, the first storage medium interface and the second storage medium interface, and is utilized for copying data from the first storage medium to the second storage medium without passing through the host interface. | 12-30-2010 |
20110264885 | CONTROLLING CIRCUIT APPLICABLE IN PHYSICAL STORAGE DEVICE AND RELATED METHOD - A controlling circuit applicable in a physical storage device includes: a dividing circuit coupled to the physical storage device for dividing a storage capacity of the physical storage device into a plurality of divided storage areas, wherein a divided storage capacity of each divided storage area is not larger than the capacity corresponding to the largest address generated by an operating system; and a feedback circuit coupled to the dividing circuit for feeding back the plurality of divided storage areas to the operating system such that the operating system regards the plurality of divided storage areas as a plurality of independent physical storage devices. | 10-27-2011 |
20110283079 | DATA PROCESSING DEVICE APPLYING FOR STORAGE DEVICE, DATA ACCESSING SYSTEM AND RELATED METHOD - A data processing device applying for a storage device includes: a first interface circuit coupled to the storage device; a processing circuit coupled to the first interface circuit for reading a control code from a divided storage area in the storage device, and executing the control code to generate a storage capacity of the storage device; and a second interface circuit coupled to the processing circuit for feeding the storage capacity back to an operating system such that the operating system regards the storage capacity as a usable capacity of the storage device. | 11-17-2011 |
Patent application number | Description | Published |
20130169338 | CLOCK GENERATOR AND METHOD OF GENERATING CLOCK SIGNAL - A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal. | 07-04-2013 |
20130171953 | CLOCK GENERATOR WITH FREQUENCY ERROR COMPENSATION AND MOBILE DEVICE USING THE SAME - A clock generator for a mobile device, capable of operating in one of a full-power mode and a low-power mode according to a standby signal to generate a high-frequency clock signal and a low-frequency clock signal is disclosed. The clock generator includes a crystal oscillator, for generating an oscillation signal of a specific frequency according to the power mode of the clock generator; a frequency division block, for dividing the oscillation signal by a specific divisor according to the power mode of the clock generator to generate the low-frequency clock signal; and a buffer block, for amplifying the oscillation signal to generate the high-frequency clock signal; wherein during each power mode, a frequency of the low-frequency clock signal is substantially the same. | 07-04-2013 |
20130188568 | WIRELESS COMMUNICATION APPARATUSES AND RELATED METHODS - An embodiment of the invention provides a method to be performed by a first wireless communication apparatus in communicating with a second wireless communication apparatus. First, the first wireless communication apparatus determines whether a plurality of sub-channels are simultaneously available for the second wireless communication apparatus. Then, the first wireless communication apparatus simultaneously uses the sub-channels to transmit a plurality of divergent copies of a data segment to the second wireless communication apparatus, respectively, if the sub-channels are simultaneously available for the second wireless communication apparatus. | 07-25-2013 |
20130232373 | METHOD FOR PERFORMING REAL TIME CLOCK CALIBRATION THROUGH FRAME NUMBER CALCULATION, AND ASSOCIATED APPARATUS - A method and apparatus for performing real time clock (RTC) calibration through frame number calculation are provided, where the method is applied to an electronic device. The method includes the steps of: before power failure of the electronic device occurs, obtaining an original time value from an RTC of the electronic device and storing the original time value and a frame number of a first frame into a storage unit; and after the electronic device is powered on since elimination of the power failure, obtaining a frame number of a second frame and performing at least one calculation operation according to the frame number of the second frame, the frame number of the first frame, and the original time value to determine a calibrated time value of the RTC, and updating the RTC with at least one of the calibrated time value and a derivative of the calibrated time value. | 09-05-2013 |
20140038538 | METHOD AND TELECOMMUNICATIONS DEVICE FOR ANALYZING MULTIPLE CARRIERS IN RADIO FREQUENCY SIGNAL - An embodiment of the invention provides a method of processing a radio frequency (RF) signal. According to the embodiment, the RF signal is first synthesized with a synthesis signal to generate a synthesized signal. Then, the synthesized signal is filtered with a filtering bandwidth to generate a filtered signal. Next, the filtered signal is converted into digital data. Then, the digital data is processed to analyze a plurality of carriers within the filtering bandwidth as presented in the RF signal. | 02-06-2014 |
Patent application number | Description | Published |
20120267656 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of fabricating a light emitting device comprising: providing a substrate; forming an epitaxial stack on the substrate wherein the epitaxial stack comprising a first conductivity semiconductor layer, an active layer and a second conductivity semiconductor layer; forming a mesa on the epitaxial stack to expose partial of the first conductivity semiconductor layer; layer and etching the surface of the first conductivity semiconductor layer and forming a least one rough structure on the surface of the first conductivity semiconductor layer wherein the first conductivity semiconductor layer is sandwiched by the substrate and the active layer. | 10-25-2012 |
20130292643 | LIGHT-EMITTING DEVICE - A light-emitting device comprising: a light-emitting stacked layer having a first conductivity type semiconductor layer; a light-emitting layer formed on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer formed on the light-emitting layer; a transparent conductive oxide layer formed on the second conductivity type semiconductor layer wherein the transparent conductive oxide layer having a first portion and a second portion and the upper surface of the transparent conductive oxide layer is a textured surface; a first electrode formed on the second portion of the transparent conductive oxide layer, and a second electrode formed on the first conductivity type semiconductor layer; a planarization layer formed on the first portion of the transparent conductive oxide layer, and the second electrode; and a reflective layer formed on the planarization layer that is devoid of the first electrode and the second electrode. | 11-07-2013 |
20130307002 | LIGHT EMITTING DEVICE WITH REFLECTIVE ELECTRODE - A light-emitting device comprises a semiconductor light emitting stack and an electrode on the semiconductor light emitting stack, wherein the electrode comprises a mirror layer, an adhesion layer inserted between the mirror layer and the semiconductor light emitting stack, a bonding layer, and a barrier layer inserted between the mirror layer and the bonding layer and covers the mirror layer to prevent the mirror layer reacting with the bonding layer, wherein the barrier layer comprises a first pair of different metals. | 11-21-2013 |
20140048830 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of fabricating a light-emitting device comprising steps of: providing a substrate, an active layer, and a first semiconductor layer between the substrate and the active layer; removing part of the active layer; and forming a rough structure in the first semiconductor layer while keeping the active layer attached to the substrate. | 02-20-2014 |
20140093991 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature. | 04-03-2014 |
Patent application number | Description | Published |
20110198747 | CONDUCTIVE PILLAR STRUCTURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component formed on a semiconductor substrate is provided. The semiconductor substrate has a first surface and a second surface. The semiconductor substrate includes a plurality of devices on the first surface. A plurality of through silicon vias (TSVs) in the semiconductor substrate extends from the first surface to the second surface. A protection layer overlies the devices on the first surface of the semiconductor substrate. A plurality of active conductive pillars on the protection layer have a first height. Each of the active conductive pillars is electrically connected to at least one of the plurality of devices. A plurality of dummy conductive pillars on the protection layer have a second height. Each of the dummy conductive pillars is electrically isolated from the plurality of devices. The first height and the second height are substantially equal. | 08-18-2011 |
20120091574 | CONDUCTIVE PILLAR STRUCTURE - The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls. | 04-19-2012 |
20120098124 | SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device has a UBM (under-bump metallization) structure underlying and electrically connected to a solder bump. The UBM structure has a first metallization layer with a first cross-sectional dimension d | 04-26-2012 |
20130034956 | CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS - A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured. | 02-07-2013 |
20140117533 | Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices - Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads. | 05-01-2014 |
Patent application number | Description | Published |
20090256682 | PRODUCT MANAGING SYSTEM AND METHOD USING RFID TECHNOLOGY - A product managing system and method using RFID technology is provided. The product managing system includes an RFID tag, an RFID reader, and a server. The RFID tag is set on a product for providing a tag ID, an object type and attribute, and an event content. The RFID reader reads the RFID tag. The server obtains various information provided by the RFID tag set on the product from the RFID reader, determines the product ID according to the tag ID, determines a class of the product and whether the product is correctly combined with another product according to the object type and attribute, and determines whether a processing procedure of the product is correctly conducted according to the event content. The server finally determines whether the product is normal according to the aforementioned determinations. | 10-15-2009 |
20100157064 | OBJECT TRACKING SYSTEM, METHOD AND SMART NODE USING ACTIVE CAMERA HANDOFF - If an active smart node detects that an object leaves a center region of a FOV for a boundary region, the active smart node predicts a possible path of the object. When the object gets out of the FOV, the active smart node predicts the object appears in a FOV of another smart node according to the possible path and a spatial relation between cameras. The active smart node notifies another smart node to become a semi-active smart node which determines an image characteristic similarity between the object and a new object and returns to the active smart node if a condition is satisfied. The active smart node compares the returned characteristic similarity, an object discovery time at the semi-active smart node, and a distance between the active smart node and the semi-active smart node to calculate possibility. | 06-24-2010 |
20100167703 | UBIQUITOUS PROXY MOBILE SERVICE METHOD AND SYSTEM AND COMPUTER RECORDABLE STORAGE MEDIUM FOR THE METHOD - A ubiquitous proxy mobile service method and system is disclosed. When a mobile device is near a dissemination medium, group data and individual data transmitted by at least one ubiquitous proxy transmission interface of the dissemination medium are read by a ubiquitous proxy receiving interface of the mobile device. A screen of the mobile device displays an interaction icon corresponding to the ubiquitous proxy according to the group data and the individual data. Uniform resource locator data in the individual data of the ubiquitous proxy corresponding to the interaction icon is read when the interaction icon is activated. A redirect operation is performed according to the uniform resource locator data to obtain a corresponding network service. | 07-01-2010 |
20100303056 | PROBABILITY TIME DIVISION MULTIPLEXING POLLING METHOD AND WIRELESS IDENTIFIER READER CONTROLLER THEREOF - Exemplary embodiments of the present invention illustrate a probability time division multiplexing polling method and a wireless identifier reader controller thereof. The probability time division multiplexing polling method is used to control a plurality of wireless identifier readers to be turned on or off. First, one of the wireless identifier readers is randomly selected according to a probability model, wherein the probability model presents the probabilities for detecting an identifier tag of the wireless identifier readers. Then, the selected wireless identifier reader is turned on for a predetermined time period. | 12-02-2010 |
Patent application number | Description | Published |
20120163107 | MEMORY DEVICE CAPABLE OF OPERATION IN A BURN IN STRESS MODE, METHOD FOR PERFORMING BURN IN STRESS ON A MEMORY DEVICE, AND METHOD FOR DETECTING LEAKAGE CURRENT OF A MEMORY DEVICE - Activate one active word line of two active word lines formed between two isolation word lines to a logic-high voltage, and float another active word line of the two active word lines. Then activate a plurality of first memory cells corresponding to the active word line having the logic-high voltage to a logic “1” voltage, and write a logic “0” voltage to a plurality of second memory cells corresponding to the floating active word line. Then write the logic “1” voltage to a plurality of bit lines. Then, suspend for charge sharing for a third predetermined time. Finally, read a voltage of the floating active word line to check if any leakage path exists between the floating active word line and the active word line having the logic-high voltage. | 06-28-2012 |
20120254470 | CONNECTOR APPLIED TO A PORTABLE DEVICE AND METHOD OF CONNECTING A PORTABLE DEVICE WITH AN EXTERNAL DEVICE - A connector applied to a portable device includes a wireless module, a connection module, at least one connection socket, a controller, and a memory. The wireless module is used for establishing a wireless connection between the portable device and the connector. The connection module is used for communicating with an external device. The at least one connection socket is used for connecting the connection module with the external device. The controller is coupled between the wireless module and the connection module for transmitting data between the wireless module and the connection module and executing commands to control the wireless module and the connection module. The memory is used for storing the commands required for the controller and is used as a data register to boost a data transmission rate between the portable device and the external device. | 10-04-2012 |
20120326219 | DYNAMIC MEMORY STRUCTURE - A dynamic memory structure includes a strip semiconductor material disposed on a substrate, a gate standing astride the strip semiconductor material and dividing the strip semiconductor material into a source terminal, a drain terminal and a channel region wherein a source width of the source terminal is larger than or equal to a channel width, a dielectric layer sandwiched between the gate and the strip semiconductor material, and a capacitor unit disposed on the substrate and including the source terminal serving as a lower electrode. | 12-27-2012 |
20130087839 | DYNAMIC MEMORY STRUCTURE - A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal. | 04-11-2013 |
20130088907 | TRANSISTOR CIRCUIT LAYOUT STRUCTURE - A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an independent second block, a bit line disposed on the source terminal and on the drain terminal or embedded in the substrate, a word line disposed on the first block, and a back line disposed on the second block. The horizontal level of the back line is different from that of the bit line and the word line. | 04-11-2013 |
Patent application number | Description | Published |
20080282107 | Method and Apparatus for Repairing Memory - Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit. | 11-13-2008 |
20090063918 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines. | 03-05-2009 |
20100149893 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 06-17-2010 |
20110019487 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line. | 01-27-2011 |
20110216607 | METHOD AND APPARATUS FOR PROTECTION OF NON-VOLATILE MEMORY IN PRESENCE OF OUT-OF-SPECIFICATION OPERATING VOLTAGE - A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. | 09-08-2011 |
20120243348 | Method and Apparatus of Changing Device Identification Codes of a Memory Integrated Circuit Device - In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. | 09-27-2012 |
20120262987 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 10-18-2012 |
20120262988 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block. | 10-18-2012 |
20130214820 | APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch. | 08-22-2013 |
20140160870 | METHOD AND APPARATUS OF CHANGING DEVICE IDENTIFICATION CODES OF A MEMORY INTEGRATED CIRCUIT DEVICE - In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code. | 06-12-2014 |
20140219026 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 08-07-2014 |
Patent application number | Description | Published |
20080288261 | METHOD FOR DYNAMICALLY ADJUSTING AUDIO DECODING PROCESS - A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval. | 11-20-2008 |
20090240357 | METHOD FOR FINDING OUT THE FRAME OF A MULTIMEDIA SEQUENCE - An electronic device is provided comprising a multimedia play unit and a processor. The processor receives a multimedia sequence, acquires a first bitrate of a first frame header from the received multimedia sequence, predicts a first length of a first frame comprising the first frame header by a formula employing at least parameters comprising the first bitrate and a proportion of a second length to a second bitrate of a second frame header prior to the first frame header, and directs the multimedia play unit to play frame data of the first frame according to the predicted first length of the first frame. | 09-24-2009 |
20110099020 | Method for Dynamically Adjusting Audio Decoding Process - A method for dynamically arranging DSP tasks. The method comprises receiving an audio bit stream, checking a remaining execution time as the DSP transforms the audio information into spectral information, simplifying the step of transforming the audio information when the DSP detects that the remaining execution time is shorter then a predetermined interval, and skipping one section of the audio information and decoding the remaining section when the execution time is less than a predetermined interval. | 04-28-2011 |
Patent application number | Description | Published |
20110048479 | CONTROL STRUCTURE FOR AUTOMATICALLY OPENED AND CLOSED UMBRELLA - An improved control structure for automatically opened and closed umbrella is provided. The control structure contains a one-way wheel linked to a string of a bullet head or an upper nest, and further contains a locking arm and a positioning arm. When the umbrella is compressed, a vertical section of the locking arm moves towards and presses against the one-way wheel's ratchets. As such, if the umbrella is accidentally released during its closing operation, the one-way wheel is locked by the locking arm and the bullet head is therefore locked as well. The compressed shaft is then immediately positioned without being affected by the suddenly released opening spring. The umbrella is therefore much safer to operate. | 03-03-2011 |
20110284043 | CONTROL STRUCTURE OF SELF-OPENING/CLOSING UMBRELLA - A control structure is provided for mounting to a handle of a self-opening/closing umbrella and includes a reversal prevention wheel around which a safety rope is wound and extending through a central shaft of the umbrella with an end fixed to the reversal prevention wheel and an end fixed to a crown. A locking member that includes a pawl bar and an operation bar is arranged above the reversal prevention wheel. When The umbrella is being compressed and closed, the pawl bar engages a toothed surface of the reversal prevention wheel, whereby when errors occur in the closing of the umbrella, reversed rotation of the wheel is prevented by the pawl bar and the safety rope connected to the reversal prevention wheel is prevented from extension so as to prevent the central shaft from undesired extension and instantaneous spring back of the central shaft is also prevented. | 11-24-2011 |
20120180833 | CONTROL STRUCTURE FOR AUTOMATICALLY FOLDING AND UNFOLDING UMBRELLA - An improved control structure for automatically folding and unfolding umbrella is provided. The control structure contains a main body whose upper and lower halves are hollow with a support base in the middle. A control piece is installed in the upper hollow space for locking the nest when the umbrella is closed and for pushing away the bullet head when the umbrella is opened. A lever having a slant block at a top end is pivotally configured on the support base. An actuating piece is configured on top of the lever. In the lower hollow space of the main body, a one-way wheel with ratchets is installed and wound with a safety string. When the umbrella is closed, the lever is prepared to engage the ratchets whenever some mishap occurs. Therefore, the umbrella is safer to operate. | 07-19-2012 |
Patent application number | Description | Published |
20120098120 | CENTRIPETAL LAYOUT FOR LOW STRESS CHIP PACKAGE - A low-stress chip package is disclosed. The package includes two substrates. The first substrate includes an array of first conductive structures in the corner area of the chip, and an array of second conductive structures in the peripheral edge area of the chip. The first and second conductive structures each has a conductive pillar having elongated cross section in the plane parallel to the first substrate and a solder bump over the pillar. The package also includes a second substrate having an array of metal traces. The elongated pillars each form a coaxial bump-on-trace interconnect with a metal trace respectively. The long axis of the elongated cross section of a pillar in the corner area of the chip points to chip's center area, and the long axis of the elongated cross section of a pillar in chip's peripheral edge area aligns perpendicular to the edge. | 04-26-2012 |
20120273934 | REDUCED-STRESS BUMP-ON-TRACE (BOT) STRUCTURES - The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased. | 11-01-2012 |
20130001778 | BUMP-ON-TRACE (BOT) STRUCTURES - A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described. | 01-03-2013 |
20130026614 | STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 01-31-2013 |
20130026619 | BUMP STRUCTURES - The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved. | 01-31-2013 |
20140110847 | BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES - A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width W | 04-24-2014 |
20140131865 | Structure and Method for Bump to Landing Trace Ratio - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 05-15-2014 |
20150084186 | BUMP STRUCTURE HAVING A SINGLE SIDE RECESS - A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill. | 03-26-2015 |
Patent application number | Description | Published |
20110089888 | Multifunctional Notebook Battery Device - A notebook computer battery pack device charges an external electrical device and powers a notebook computer. The notebook computer battery pack device includes battery cells for converting chemical energy into direct current power, a first interface connector for transferring the direct current power to a notebook computer, a second interface connector for transferring the direct current power to the external electrical device, battery management circuitry for providing circuit protection, and charging circuitry for charging the external electrical device through the second interface connector. | 04-21-2011 |
20140111245 | INTEGRATED CIRCUIT DESIGN PROTECTING DEVICE AND METHOD THEREOF - An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device. | 04-24-2014 |
20150048875 | HIGH VOLTAGE POWER CONTROL SYSTEM - A high voltage power control system comprises a microcontroller unit, an embedded non-volatile memory, and a high voltage driver. The micro controller unit is configured to control high voltage outputs of the high voltage power control system. The embedded non-volatile memory is electrically connected to the micro controller. The high voltage driver is electrically connected to the micro controller and is configured to output the high voltage outputs of the high voltage power control system. The high voltage power control system is compatible with a logic process while the embedded non-volatile memory and the high voltage power control system can still support operations of high voltage. | 02-19-2015 |
Patent application number | Description | Published |
20100090312 | Nitride semiconductor structure and method for manufacturing the same - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer. | 04-15-2010 |
20110003410 | METHOD OF MANUFACTURING A LIGHT EMITTING DIODE ELEMENT - A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector. | 01-06-2011 |
20110254044 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING A LIGHT EMITTING DEVICE - A light emitting device and a method of fabricating a light emitting device are provided. The light emitting device includes a carrier substrate, at least one epitaxy structure, a high resistant ring wall, a first electrode, and a second electrode. The epitaxy structure is disposed on the carrier substrate and includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is relatively away from the carrier substrate and the second semiconductor layer is relatively close to the carrier substrate. The high resistant ring wall surrounds the epitaxy structure and a width of the high resistant ring wall is greater than 5 μm. The first electrode is disposed between the carrier substrate and the epitaxy structure. The second electrode is disposed at a side of the epitaxy structure away from the carrier substrate. | 10-20-2011 |
20120119220 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate. | 05-17-2012 |
20130168687 | ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE - Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current. | 07-04-2013 |
Patent application number | Description | Published |
20110089447 | LIGHT-EMITING DEVICE CHIP WITH MICRO-LENSES AND METHOD FOR FABRICATING THE SAME - A light-emitting device (LED) chip is disclosed. The LED chip includes a body having a light extraction surface. The body includes semiconductor layers including an n-type region and a p-type region. A plurality of micro-lenses is directly on the light extraction surface of the body. A pair of bond pads is electrically connected to the n-type and p-type regions, respectively. A method for fabricating the LED chip and an LED package with the LED chip are also disclosed. | 04-21-2011 |
20110101405 | LIGHT-EMITTING DIODE PACKAGE - A light-emitting diode package is provided. The light-emitting diode package comprises a substrate and a first metal layer disposed over the substrate. A solder layer is disposed on the first metal layer and a light-emitting diode chip is disposed on the solder layer, wherein the light-emitting diode chip comprises a conductive substrate and a multilayered epitaxial structure formed on the conductive substrate, and wherein the conductive substrate is adjacent to the solder layer. | 05-05-2011 |
20120025387 | CHIP PACKAGE AND FABRICATING METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion. | 02-02-2012 |
20120248473 | LIGHT EMITTING SEMICONDUCTOR STRUCTURE - The invention provides a light emitting semiconductor structure, which includes a substrate; a first LED chip formed on the substrate; an adhesion layer formed on the first LED chip; and a second light emitting diode chip formed on the adhesion layer, wherein the second LED chip has a first conductive wire which is electrically connected to the substrate. | 10-04-2012 |
20140184863 | METHOD FOR CORRECTING PIXEL INFORMATION OF COLOR PIXELS ON A COLOR FILTER ARRAY OF AN IMAGE SENSOR - A method for correcting pixel information of color pixels on a color filter array of an image sensor includes: establishing an M×M distance factor table, selecting M×M pixels of the color filter array, calculating a red/green/blue-color contribution from the red/green/blue pixels to a target pixel in the selected M×M pixels, calculating a red/blue/green-color pixel performance of the target pixel, calculating a red/blue/green-color correcting factor, obtaining a corrected pixel information of each of the red/green/blue pixels, by applying the red/green/blue-color correcting factor to the measured pixel information of each of the red/green/blue pixels. | 07-03-2014 |
20140191260 | LIGHT EMITTING SEMICONDUCTOR STRUCTURE - The invention provides a light emitting semiconductor structure, which includes a substrate; a first LED chip formed on the substrate; an adhesion layer formed on the first LED chip; and a second light emitting diode chip formed on the adhesion layer, wherein the second LED chip has a first conductive wire which is electrically connected to the substrate. | 07-10-2014 |
20140362250 | METHOD FOR CORRECTING PIXEL INFORMATION OF COLOR PIXELS ON A COLOR FILTER ARRAY OF AN IMAGE SENSOR - A method for correcting pixel information of color pixels on a color filter array of an image sensor includes: establishing an M×M distance factor table, selecting M×M pixels of the color filter array, calculating a red/green/blue-color contribution from the red/green/blue pixels to a target pixel in the selected M×M pixels, calculating a red/blue/green-color pixel performance of the target pixel, calculating a red/blue/green-color correcting factor, obtaining a corrected pixel information of each of the red/green/blue pixels, by applying the red/green/blue-color correcting factor to the measured pixel information of each of the red/green/blue pixels. | 12-11-2014 |
Patent application number | Description | Published |
20110187457 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to forma signal output path and for adjusting impedance of the signal output path when the signal output path is formed. | 08-04-2011 |
20120319770 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed. The output control unit comprises a plurality of output switches for individually turning on or off the electrical connection between the output terminal and the capacitive load of the operational amplifier. | 12-20-2012 |
20140285260 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit change a value of the variable impedance of the signal output path. | 09-25-2014 |
Patent application number | Description | Published |
20090089526 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device. | 04-02-2009 |
20100299473 | SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION - A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. | 11-25-2010 |
20120131227 | SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION - A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins. | 05-24-2012 |
20130086294 | Serial Peripheral Interface and Method for Data Transmission - A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. | 04-04-2013 |