Patent application number | Description | Published |
20080288815 | Firmware assisted error handling scheme - A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system. | 11-20-2008 |
20090327684 | Apparatus and method for secure boot environment - In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a boot block stored at a first memory location, a capsule update stored at a second memory location, a startup authenticated code module to ensure the integrity of the boot block upon a restart of the processor-based system, code which is executable by the processor-based system to cause the processor-based system to validate the boot block with the startup authenticated code module upon the restart of the processor-based system, and, if the boot block is successfully validated, to validate the capsule update for the processor-based system with the startup authenticated code module. Other embodiments are disclosed and claimed. | 12-31-2009 |
20100169633 | SYSTEM AND METHOD TO SECURE BOOT BOTH UEFI AND LEGACY OPTION ROM'S WITH COMMON POLICY ENGINE - In some embodiments, the invention involves using a policy engine during boot, in the driver execution environment (DXE) phases to authenticate that drivers and executable images to be loaded are authenticated. Images to be authenticated include the operating system (OS) loader. The policy engine utilizes a certificate database to hold valid certificates for third party images, according to platform policy. Images that are not authenticated are not loaded at boot time. Other embodiments are described and claimed. | 07-01-2010 |
20130151569 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 06-13-2013 |
20130254602 | FIRMWARE ASSISTED ERROR HANDLING SCHEME - A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system. | 09-26-2013 |
20130304980 | AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM - A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM. | 11-14-2013 |
20140053024 | COMPUTING PLATFORM WITH INTERFACE BASED ERROR INJECTION - In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, hardware component error injection. | 02-20-2014 |
20140059368 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 02-27-2014 |
20140082262 | APPARATUS, METHOD AND SYSTEM THAT STORES BIOS IN NON-VOLATILE RANDOM ACCESS MEMORY - A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS. | 03-20-2014 |
20140258701 | COMPUTING PLATFORM PERFORMANCE MANAGEMENT WITH RAS SERVICES - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface. | 09-11-2014 |
20150178142 | EXCHANGE ERROR INFORMATION FROM PLATFORM FIRMWARE TO OPERATING SYSTEM - A computing system can include a platform firmware to monitor hardware errors and to notify an operating system when a corrective action is to be performed to address a hardware error. The computing system can also include an extended error log to describe a hardware error. The computing system can further include an action record to direct the operating system to perform the corrective action to address the hardware error. | 06-25-2015 |
Patent application number | Description | Published |
20080239772 | SWITCHED CAPACITOR CONVERTERS - A switched capacitor converter has a supply voltage input, an output circuit with one or more load capacitors, a semiconductor switch network. The switch network is connected at a switch junction point and across the voltage input, and has one or more pairs of said first and second switches. Each pair of switches is associated with one of the load capacitors and each pair is connected in series. The converter also has a charging capacitor network connected across the semiconductor switch network and across the voltage input. The charging capacitor network has one or more charging capacitors and inductances connected between the switch junction point and the output circuit. Each of the charging capacitors and inductances is associated with one of the load capacitors. The load capacitors are each charged by the associated charging capacitor when the associated first switch is closed and the associated second switch is open. And the load capacitors are each discharged by the associated inductance when the associated first switch is closed and the associated second switch is open. | 10-02-2008 |
20090085553 | Reconfigurable battery pack - In some embodiments, a system comprises a voltage regulator having two or more inputs with each having its own input voltage level and at least one switch to select between the input voltage levels, a configurable battery pack comprising at least two cells and at least one switch capable of configuring the battery in either a series configuration or a parallel configuration, a detector to measure a load parameter on the system; and a controller to send a signal to the at least one switch to select between the input voltage levels based on the measured load parameter. | 04-02-2009 |
20110085486 | SYSTEM AND METHOD FOR CONTROLLING HOME NETWORK DEVICES USING MULTICAST ENABLED REMOTE CONTROLS - A system, method, and article of manufacture for controlling home network devices using a multicast enabled remote control. The system includes a plurality of home network devices capable of receiving and/or transmitting multicast input and/or output signals and a home gateway to receive audio/video signals generated outside of the home and to transform the audio/video signals into multicast output signals. The system also includes a multicast enabled remote control to detect, aggregate, store and display all audio/video multicast output signals on the multicast enabled remote control, to enable a user to redirect an audio/video multicast output signal to one or more of the plurality of home network devices capable of receiving multicast input signals, and to control the plurality of home network devices capable of receiving and/or transmitting multicast input and/or output signals. Other embodiments may be described and claimed. | 04-14-2011 |
20110093903 | SYSTEM AND METHOD FOR CONTROLLING HOME NETWORK DEVICES USING MULTICAST ENABLED REMOTE CONTROLS - A system, method, and article of manufacture for controlling home network devices using a multicast enabled remote control. The system includes a plurality of home network devices capable of receiving and/or transmitting multicast input and/or output signals and a home gateway to receive audio/video signals generated outside of the home and to transform the audio/video signals into multicast output signals. The system also includes a multicast enabled remote control to detect, aggregate, store and display all audio/video multicast output signals on the multicast enabled remote control, to enable a user to redirect an audio/video multicast output signal to one or more of the plurality of home network devices capable of receiving multicast input signals, and to control the plurality of home network devices capable of receiving and/or transmitting multicast input and/or output signals. Other embodiments may be described and claimed. | 04-21-2011 |
20110103285 | SYSTEM AND METHOD FOR CONTROLLING HOME NETWORK DEVICES USING MULTICAST ENABLED REMOTE CONTROLS - A system, method, and article of manufacture for controlling home network devices using a multicast enabled remote control. The system includes a plurality of home network devices capable of receiving and/or transmitting multicast input and/or output signals and a home gateway to receive audio/video signals generated outside of the home and to transform the audio/video signals into multicast output signals. The system also includes a multicast enabled remote control to detect, aggregate, store and display all audio/video multicast output signals on the multicast enabled remote control, to enable a user to redirect an audio/video multicast output signal to one or more of the plurality of home network devices capable of receiving multicast input signals, and to control the plurality of home network devices capable of receiving and/or transmitting multicast input and/or output signals. Other embodiments may be described and claimed. | 05-05-2011 |
20130257410 | LOW FREQUENCY CONVERTERS HAVING ELECTROCHEMICAL CAPACITORS - In one embodiment of the invention, a low frequency converter is described that includes a first electrochemical capacitor to charge to an input voltage and a second electrochemical capacitor that is coupled to the first electrochemical capacitor. The second electrochemical capacitor is associated with an output voltage of the low frequency converter. Each electrochemical capacitor may have a capacitance of at least one millifarad (mF) and a switching frequency that is less than one kilohertz. | 10-03-2013 |
20140239719 | SWITCHED CAPACITOR BASED MULTIPLE OUTPUT FIXED RATIO CONVERTER - Systems and methods of generating output multiple voltages may include connecting a first low pass filter to a switched capacitor voltage divider at the first junction point. The switched capacitor voltage divider may be configured to receive an input voltage and to generate a first output voltage. The first low pass filter may be associated with a second output voltage. The first junction point may be positioned between a first switch and a second switch of the switched capacitor voltage divider. | 08-28-2014 |
20160006350 | TECHNIQUES FOR REDUCING SWITCHING NOISE AND IMPROVING TRANSIENT RESPONSE IN VOLTAGE REGULATORS - Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed. | 01-07-2016 |
Patent application number | Description | Published |
20140256111 | Nonvolatile Memory Elements - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. | 09-11-2014 |
20140361236 | ALD processing techniques for forming non-volatile resistive switching memories - ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer. | 12-11-2014 |
20150034896 | Resistive-Switching Nonvolatile Memory Elements - Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. | 02-05-2015 |
20150056748 | Methods for Forming Resistive Switching Memory Elements by Heating Deposited Layers - Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements. | 02-26-2015 |
20150097153 | Non-volatile Resistive-Switching Memories - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm | 04-09-2015 |
20150137064 | Reduction of forming voltage in semiconductor devices - This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results. | 05-21-2015 |
20150255716 | Non-volatile Resistive-Switching Memories - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm | 09-10-2015 |
Patent application number | Description | Published |
20160032453 | SYSTEMS AND METHODS FOR VAPOR DELIVERY - A vapor delivery system includes an ampoule to store liquid precursor and a heater to partially vaporize the liquid precursor. A first valve communicates with a push gas source and the ampoule. A second valve supplies vaporized precursor to a heated injection manifold. A valve manifold includes a first node in fluid communication with an outlet of the heated injection manifold, a third valve having an inlet in fluid communication with the first node and an outlet in fluid communication with vacuum, a fourth valve having an inlet in fluid communication with the first node and an outlet in fluid communication with a second node, a fifth valve having an outlet in fluid communication with the second node, and a sixth valve having an outlet in fluid communication with the second node. A gas distribution device is in fluid communication with the second node. | 02-04-2016 |
20160035566 | METHODS AND APPARATUSES FOR SHOWERHEAD BACKSIDE PARASITIC PLASMA SUPPRESSION IN A SECONDARY PURGE ENABLED ALD SYSTEM - Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed precursor by purging the processing chamber with a primary purge gas, and thereafter reacting adsorbed film precursor while a secondary purge gas is flowed into the processing chamber, resulting in the formation of a film layer on the substrate. The secondary purge gas may include a chemical species having an ionization energy and/or a disassociation energy equal to or greater than that of O | 02-04-2016 |
20160052651 | FILL ON DEMAND AMPOULE - Methods and apparatus for use of a fill on demand ampoule are disclosed. The fill on demand ampoule may refill an ampoule with precursor concurrent with the performance of other deposition processes. The fill on demand may keep the level of precursor within the ampoule at a relatively constant level. The level may be calculated to result in an optimum head volume. The fill on demand may also keep the precursor at a temperature near that of an optimum precursor temperature. The fill on demand may occur during parts of the deposition process where the agitation of the precursor due to the filling of the ampoule with the precursor minimally effects the substrate deposition. Substrate throughput may be increased through the use of fill on demand. | 02-25-2016 |
20160056032 | METHODS AND APPARATUSES FOR STABLE DEPOSITION RATE CONTROL IN LOW TEMPERATURE ALD SYSTEMS BY SHOWERHEAD ACTIVE HEATING AND/OR PEDESTAL COOLING - Disclosed are methods of depositing films of material on semiconductor substrates. The methods may include flowing a film precursor into a processing chamber through a showerhead substantially maintained at a first temperature, and adsorbing the film precursor onto a substrate held on a substrate holder such that the precursor forms an adsorption-limited layer while the substrate holder is substantially maintained at a second temperature. The first temperature may be at least about 10° C. above the second temperature, or the first temperature may be at or below the second temperature. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed film precursor, and thereafter reacting adsorbed film precursor to form a film layer. Also disclosed herein are apparatuses having a processing chamber, a substrate holder, a showerhead, and one or more controllers for operating the apparatus to employ the foregoing film deposition techniques. | 02-25-2016 |
20160090650 | METHOD AND APPARATUS FOR RF COMPENSATION IN PLASMA ASSISTED ATOMIC LAYER DEPOSITION - The embodiments herein relate to methods, apparatus, and systems for depositing film on substrates. In these embodiments, the substrates are processed in batches. Due to changing conditions within a reaction chamber as additional substrates in the batch are processed, various film properties may trend over the course of a batch. Disclosed herein are methods and apparatus for minimizing the trending of film properties over the course of a batch. More specifically, film property trending is minimized by changing the amount of RF power used to process substrates over the course of the batch. Such methods are sometimes referred to as RF compensation methods. | 03-31-2016 |