Patent application number | Description | Published |
20090251226 | LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP - A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal. | 10-08-2009 |
20110296221 | METHOD AND SYSTEM FOR INTEGRATED CIRCUIT POWER SUPPLY MANAGEMENT - A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block. | 12-01-2011 |
20120176188 | POWER SWITCH FOR DECREASED RAMP RATE - A power switch for an integrated circuit provides a stepped profile supply potential. A supply potential generation block generates the stepped profile output supply to control the ramp rate of the output in order to prevent a false trigger of electrostatic discharge at the pads of the integrated circuit. | 07-12-2012 |
20130047016 | SEMICONDUCTOR DEVICE WITH WAKE-UP UNIT - A semiconductor device having a low power mode includes a buffer circuit associated with an interface pad, a power management controller (PMC), and a wakeup unit for waking up a part of the device from the low power mode. The buffer circuit is disabled in the low power mode by asserting a power on reset (POR) signal associated with the PMC. A wakeup signal is generated and provided to the wakeup unit from an analog power supply associated with the buffer circuit. | 02-21-2013 |
20130093505 | ON-CHIP VOLTAGE REGULATOR - A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC. | 04-18-2013 |
20130275936 | INTEGRATED CIRCUIT POWER MANAGEMENT VERIFICATION METHOD - A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value. | 10-17-2013 |
20130339761 | POWER MANAGEMENT SYSTEM FOR ELECTRONIC CIRCUIT - A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal. | 12-19-2013 |
20140122010 | LCD DRIVER VERIFICATION SYSTEM - A system and method for verifying the electrical behavior of a liquid crystal display (LCD) driver circuit connected to LCD segments of an electronic circuit includes generating test patterns for verifying the LCD driver circuit. The LCD driver circuit generates LCD stimuli in the form of electrical current based on the test patterns. The current is applied to front and back planes of each LCD segment. Root mean square (RMS) voltages of each LCD segment are determined and compared with predetermined threshold values to verify the state of each LCD segment. | 05-01-2014 |
20140333133 | INTEGRATED CIRCUIT POWER MANAGEMENT MODULE - An integrated circuit includes a set of electronic circuits, a voltage regulator, and a power management module. The power management module includes a set of dummy circuits connected to the set of electronic circuits, a control signal generator, a counter and a shift register. The control signal generator generates a control signal based on the current consumption of the set of electronic circuits dropping below a threshold value over a predefined period of time. The counter generates a count signal for a predetermined time period when the control signal is activated. The shift register receives the count signal, enables the dummy circuits when the count signal is received, and disables the dummy circuits in a daisy chain fashion during the predetermined time period. | 11-13-2014 |
20140333287 | SYSTEM FOR MEASURING POWER CONSUMPTION OF INTEGRATED CIRCUIT - An integrated circuit includes electronic components, a voltage regulator for generating a control voltage, and a power consumption measurement module. The power consumption measurement module is connected to the voltage regulator and includes an analog-to-digital converter (ADC) for converting the control voltage to multiple digital control voltage samples, an averaging module for averaging the digital control voltage samples, and a current profiling module for receiving the averaged control voltage data and determining an average current from averaged control voltage data. The average current represents power consumption of the integrated circuit. | 11-13-2014 |
20140351615 | INTEGRATED CIRCUIT WAKE-UP CONTROL SYSTEM - An integrated circuit (IC) that operates in high and low power modes includes high and low power regulators, first and second sets of circuits, a switch connecting the high power regulator and the second set of circuits, and a wake-up control system. The wake-up control system includes a state machine that enables the high power regulator when the IC is in the high power mode, and enables the low power regulator when the IC is in the low power mode. The switch is closed when the high power regulator reaches a first threshold voltage. The state machine operates on a low frequency clock signal when the IC is in the low power mode and during wake-up, and on a high frequency clock signal in the high power mode after the switch is closed. | 11-27-2014 |