Patent application number | Description | Published |
20090002114 | INTEGRATED INDUCTOR - An integrated inductor has a winding. The winding includes a first level metal layer inlaid in a first dielectric layer, a second level metal layer inlaid in a second dielectric layer above the first dielectric layer, and a first line-shaped via structure inlaid in a slot of a third dielectric layer interposed between the first and second dielectric layers for interconnecting the first and second level metal layers. | 01-01-2009 |
20090261937 | INTEGRATED INDUCTOR - An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well. | 10-22-2009 |
20100295150 | SEMICONDUCTOR DEVICE WITH OXIDE DEFINE DUMMY FEATURE - A semiconductor device includes a substrate, an inductor wiring pattern on the substrate, and at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern. | 11-25-2010 |
20110133308 | SEMICONDUCTOR DEVICE WITH OXIDE DEFINE PATTERN - A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate. | 06-09-2011 |
20120126368 | Semiconductor Package - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer | 05-24-2012 |
20130002375 | TRANSMISSION LINE STRUCTURE WITH LOW CROSSTALK - A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer. | 01-03-2013 |
20150194403 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level. | 07-09-2015 |
20160056105 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer. | 02-25-2016 |