Patent application number | Description | Published |
20090125471 | Event detection and method and system - An event detection method is disclosed. At least one most adaptable life cycle model is generated according to at least one historical event data, at least one nutrition growing function, and at least one firing point rule. Event data is received and a strength value thereof is calculated according to a life cycle model corresponding to the event data. It is determined whether an event firing point is achieved according to the strength value variation. If the event firing point is achieved, an event corresponding to the event data is sent. The event detection method enhances the ability of event tracking and development so event firing is more accurate to fit real event occurring situations, realize event evolution, and filter false alarms. | 05-14-2009 |
20100214198 | DISPLAY DEVICE - A display device includes a display panel, a flexible printed circuit and a back light module. The flexible printed circuit is suitable for supporting the driving element and is electrically connected to the display panel. The back light module includes at least one light source, a first frame and a second frame. The light source is disposed between the first frame and the second frame, and the display panel and the flexible printed circuit are disposed at one side of the first frame, wherein the first frame has at least an opening, the second frame has a element contacting surface, the driving element is disposed on the flexible printed circuit, and the element contacting surface protrudes from the opening for being connected to the driving element. | 08-26-2010 |
20100214199 | DISPLAY DEVICE FOR PREVENTING ELECTROMAGNETIC INTERFERENCE - A display device includes a display panel, a back light module, a printed circuit board and a ground slice. The back light module includes a first frame, a second frame and a light source disposed between the first frame and the second frame. The first frame has a first side plate having an opening, and the second frame has a second side plate opposite to the first side plate. The printed circuit board includes a control circuit electrically connected to the display panel. The printed circuit board is disposed at a side of the back light module, and the control circuit is disposed at the outer side of the first side plate and the second side plate, such that the control circuit is opposite to the second side plate through the opening. The ground slice is connected between the control circuit and the second side plate through the opening. | 08-26-2010 |
20110079807 | LIGHT-EMITTING DIODE STRUCTURE - A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block. | 04-07-2011 |
20110119373 | SERVICE WORKFLOW GENERATION APPARATUS AND METHOD - A service workflow generation apparatus, having a quality of service (QoS) monitor for obtaining a plurality of real time QoS values respectively corresponding to a plurality of service elements on the web. A QoS calculation module generates a plurality of possible service workflows composed of the service elements and a plurality of overall QoS values of the possible service workflows based on the real time QoS values by using a Modified Heuristic Algorithm. A service workflow selection module dynamically selects a service workflow from the possible service workflows according to the overall QoS value. | 05-19-2011 |
Patent application number | Description | Published |
20080246057 | Silicon layer for stopping dislocation propagation - A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices. | 10-09-2008 |
20100127898 | INPUT APPARATUS, INPUT METHOD AND ELECTRONIC APPARATUS USING THE SAME - An input apparatus, an input method and an electronic apparatus are provided. The input apparatus includes a signal generating module and a processing module. The signal generating module generates a plurality of input signals by executing multi-direction operations. The processing module receives two signals of the input signals which are successively generated by the signal generating module, thus generating a control signal. The control signal corresponds to one of a plurality of characters. Therefore, the input apparatus can be more conveniently used by users to input characters by executing multi-direction operations. | 05-27-2010 |
20110073952 | Controlling the Shape of Source/Drain Regions in FinFETs - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. | 03-31-2011 |
20110199370 | Image Processing Method for Feature Retention and the System of the Same - The present invention discloses an image processing method for feature retention associated with averaging processes. The image processing method comprises: scaling and aligning a plurality of image data for acquiring feature information; determining a plurality of two-dimensional feature label points according to the feature information for generating at least one Bezier curve; utilizing the at least one Bezier curve to generate at least one Bezier tube and performing Bezier tube fitting for generating result of Bezier tube fitting; deforming the plurality of image data according to the Bezier tube or the result of Bezier tube fitting for generating a plurality of deformed image data; and averaging the plurality of deformed image data for generating feature-preserved average image data. The present invention also provides an image processing system, a computer readable storage medium, and a computer program product, for implementing the image processing method. | 08-18-2011 |
20110210404 | Epitaxy Profile Engineering for FinFETs - A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin. | 09-01-2011 |
20130001705 | Epitaxy Profile Engineering for FinFETs - A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin. | 01-03-2013 |
20130038550 | MULTI-PROTECTION TOUCH LOCK - A multi-protection touch lock has a lock body and an unlocking panel connecting to the lock body. The lock body has a control mechanism, a locking unit connecting to the control mechanism, and at least one displaying unit connecting to the control unit, and at least one connection interface connecting to the displaying unit. The at least one unlocking panel has at least one transmission interface connecting to the at least one connection interface, and at least one operating unit connecting to the at least one transmission interface. The lock can be located at the predetermined position to control the door access, vehicle actuation and the use of electrical appliances. When unlocking, the unlocking panel comes to in contact with the lock and the correct password is input via the unlocking panel. After the unlocking action is completed, the unlocking panel is removed from the predetermined position. | 02-14-2013 |
20130044257 | MOBILE DEVICE WITH SIDE-MOUNTED CAMERA MODULE - The present disclosure relates to a mobile device provided with a camera module that is detachably received in a side of the device body. Particularly, the camera module is hidden inside the device body when not in use and can be drawn out from the side of the device body when in use. Since the camera module is not affixed permanently to the device, the detachable camera module can be used in small confined areas with expanded photo-capturing scope and angle. | 02-21-2013 |
20130089959 | Controlling the Shape of Source/Drain Regions in FinFETs - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. | 04-11-2013 |
20130122674 | Silicon Layer for Stopping Dislocation Propagation - A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices. | 05-16-2013 |
20140092567 | CLIP ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME - A clip assembly includes a seat having a surrounding wall with a receiving hole, and a locking mechanism proximate to the surrounding wall and including a pair of movable levers. Each movable lever has an engaging portion movably inserted into the receiving hole, and a driven portion. A drive unit has a button that is moved to a pressed position, where the driven portions are pushed to move away from each other and out of the receiving hole. A clip mechanism includes a connection body received in the receiving hole and having two connecting holes to respectively engage the engaging portions. The engaging portions are disengageable from the connecting holes by pressing the button. | 04-03-2014 |
20140127886 | Reducing Pattern Loading Effect in Epitaxy - A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions. | 05-08-2014 |
20150137183 | Controlling the Shape of Source/Drain Regions in FinFETs - An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. | 05-21-2015 |
Patent application number | Description | Published |
20100134234 | SHIFT REGISTER APPARATUS - A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof. | 06-03-2010 |
20110024801 | TRANSISTORS HAVING A COMPOSITE STRAIN STRUCTURE, INTEGRATED CIRCUITS, AND FABRICATION METHODS THEREOF - A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate. | 02-03-2011 |
20110042729 | METHOD FOR IMPROVING SELECTIVITY OF EPI PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 02-24-2011 |
20110108894 | METHOD OF FORMING STRAINED STRUCTURES IN SEMICONDUCTOR DEVICES - The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material. | 05-12-2011 |
20110147846 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 06-23-2011 |
20120015459 | Thermal Leveling for Semiconductor Devices - A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution. | 01-19-2012 |
20120181625 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions. | 07-19-2012 |
20120205715 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved lightly doped source/drain features and source/drain features in the semiconductor device. Semiconductor device with the improved lightly doped source/drain features and source/drain features may prevent or reduce defects and achieve high strain effect. In at least one embodiment, the lightly doped source/drain features and source/drain features comprises the same semiconductor material formed by epitaxial growth. | 08-16-2012 |
20120268924 | LIGHT GUIDE UNIT AND OPTICAL DEVICES USING THE SAME - A light guide unit provided in this disclosure is used for performing a reversible optical conversion process on a light source. In an embodiment, the light guide unit is used for converting a planar light source into at least a linear light source, and then further to be converted into one point light source, while allowing beams emitted from the point light source to be guided and shot to a specific position by the use of a light-guiding element. Moreover, in another embodiment, the light guide unit is used for converting at least one point light source into at least a linear light source, and then further to be converted into a planar light source for emitting light. The light guide unit can be adapted for various applications, such as optical devices for illumination, entertainment, decoration or ornaments. | 10-25-2012 |
20120304713 | OPTICAL DEVICE - An optical device includes: a lock having a locking unit and an operation unit having at least a sensor; and a key configured to correspond to the lock. The key includes an unlocking unit having at least a light-guiding element for transmitting light between the operation unit and the unlocking unit. The operation unit is activated to unlock the locking unit after the sensor detects and recognizes the transmitted light. After encoding, the optical device of the present invention cannot be reproduced and the encoded light beam will not be intercepted and decoded easily so as to satisfy our security demands. Further, the structure of the optical device of the present invention does not decay easily. Therefore, the present invention has an excellent anti-theft effect and a reduced production cost. | 12-06-2012 |
20130299876 | Method For Improving Selectivity Of EPI Process - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process. | 11-14-2013 |
20140017971 | Optical Toy - An optical toy is disclosed. The optical toy includes a frame, at least one emitting part, at least one receiving part, a plurality of light guiding parts, and at least one power source. The frame includes a container and at least one containing structure. The emitting part is movably located on the containing structure. The emitting part includes at least one light source for emitting light. The receiving part is movably located on the containing structure. The receiving part includes a light sensor for sensing the light. The plurality of light guiding parts is located in the container for changing the direction of the light. The relative positions of the plurality of light guiding parts can be changed. The power source is located in the frame for providing power to the optical toy. | 01-16-2014 |
20140085583 | DISPLAY PANEL - A display panel includes a pixel structure that has first, second, and third sub-pixels. In the first sub-pixel, a first pixel electrode having first branches and a second pixel electrode having second branches are alternately arranged. Gap dB is defined between adjacent first and second branches. In the second sub-pixel, a third pixel electrode having third branches and a fourth pixel electrode having fourth branches are alternately arranged. Gap dG is defined between adjacent third and fourth branches. In the third sub-pixel, a fifth pixel electrode having fifth branches and a sixth pixel electrode having sixth branches are alternately arranged. Gap dR is defined between adjacent fifth and sixth branches. The gaps dB, dG, and dR at least include minimum gaps dB | 03-27-2014 |
20140209978 | DEVICES WITH STRAINED SOURCE/DRAIN STRUCTURES - A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions. | 07-31-2014 |
20140308790 | METHODS FOR MANUFACTURING DEVICES WITH SOURCE/DRAIN STRUCTURES - In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material. | 10-16-2014 |
20140349544 | Illuminable Building block - An illuminable building block is disclosed. The illuminable building block has a cell body, at least one circuit board, at least one illuminating device, at least one photo sensing device, at least one circuit control module, and at least one assembly portion. The cell body has an accommodating space, and the circuit board is located therein. The at least one illuminating device is disposed at the inner surface of the circuit board, and each photo sensing device corresponds to at least one illuminating device. The at least one circuit control module is used for illuminating the illuminating device. | 11-27-2014 |
Patent application number | Description | Published |
20090134913 | SIGNAL COMPARISON CIRCUIT - A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison. | 05-28-2009 |
20090219056 | SIGNAL DETECTION CIRCUIT WITH DEGLITCH AND METHOD THEREOF - A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal. | 09-03-2009 |
20100060345 | REFERENCE CIRCUIT FOR PROVIDING PRECISION VOLTAGE AND PRECISION CURRENT - A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage. | 03-11-2010 |
20100073045 | FREQUENCY DETECTION CIRCUIT AND DETECTION METHOD FOR CLOCK DATA RECOVERY CIRCUIT - A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal. | 03-25-2010 |
20110285728 | IMAGE PROCESSING DEVICE AND IMAGE SIGNAL PROCESSING SYSTEM - An image signal processing system is presented, which includes a computer, a master image processing device, and at least one slave image processing device. The master image processing device is used for receiving an image signal. The master image processing device includes a master signal conversion device and a master signal output device. The master signal conversion device is used for converting the image signal into an instruction signal, and the master signal output device is used for outputting the instruction signal. The slave image processing device includes a slave signal input device, a slave signal conversion device, and a GPU. The slave signal input device is used for receiving the instruction signal. The slave signal conversion device is used for selectively converting the instruction signal into an image signal according to the instruction signal. The GPU is used for receiving the image signal and generating a broadcasting signal. | 11-24-2011 |
Patent application number | Description | Published |
20110279440 | CIRCUIT FOR AMPLIFYING A DISPLAY SIGNAL TO BE TRANSMITTED TO A REPAIR LINE BY USING A NON-INVERTING AMPLIFIER AND LCD DEVICE USING THE SAME - A circuit for amplifying a display signal transmitted to a repair line by using a non-inverting amplifier is disclosed, which comprises a voltage follower, a non-inverting amplifier, a repair line, a thin film transistor (TFT) and a liquid crystal (LC) capacitor. The voltage follower is electrically connected to a data driver chip to thereby provide a display signal to the non-inverting amplifier. The non-inverting amplifier amplifies the display signal to thus obtain an amplified display signal, and transmits the amplified display signal to the TFT and the LC capacitor through the repair line. The amplified display signal is kept at a desired voltage level when the LC capacitor receives the amplified display signal. | 11-17-2011 |
20110317803 | SHIFT REGISTER CIRCUIT AND SHIFT REGISTER - An exemplary shift register circuit includes a plurality of shift registers for sequentially outputting a plurality of driving pulse signals. Among each M number of the shift registers for sequentially outputting M number of the driving pulse signals, the shift register for lastly outputting one of the M number of driving pulse signals is enabled, by (M−1) number of start pulse signals sequentially outputted from the remained (M−1) number of the shift registers, to generate the driving pulse signal. Herein, M is a positive integer greater than 2. Moreover, a circuit structure of a shift register also is provided. | 12-29-2011 |
20120038603 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural stages of shift registers. Each stage of shift register includes a pull-up circuit, a control signal generator and a voltage-stabilizing circuit. The pull-up circuit is used for charging a first node. The control signal generator is electrically connected with the first node. According to a voltage level of the first node, a corresponding control signal is outputted from an output terminal of the control signal generator. The voltage-stabilizing circuit is electrically connected with the output terminal of the control signal generator for stabilizing the control signal from the control signal generator. Some circuits of some other shift registers are controlled according to the control signal. | 02-16-2012 |
20120113068 | LCD DRIVING CIRCUIT AND RELATED DRIVING METHOD - An LCD device is configured to drive a plurality of shift register units using two clock signals having different driving abilities. Each shift register unit may thus generate a stronger signal for triggering a next-stage shift register unit, thereby improving cold-start. When the LCD device has been activated over a predetermined period of time, the driving ability of the clock signal having higher driving ability is gradually lowered, thereby reducing power consumption. | 05-10-2012 |
20120194646 | Method of Enhancing 3D Image Information Density - A method of enhancing 3D image information density, comprising providing a confocal fluorescent microscope and a rotational stage. 3D image samples at different angles are collected. A deconvolution process of the 3D image samples by a processing unit is performed. A registration process of the deconvoluted 3D image samples by the processing unit is performed. An interpolation process of the registered 3D image samples by the processing unit is performed to output a 3D image in high resolution. | 08-02-2012 |
20140085256 | CAPACITIVE TOUCH SENSOR STRUCTURE AND APPLICATIONS THEREOF - A capacitive touch sensor structure comprises a substrate, a first transmissive electrode, a first wire, a first receiving electrode and a second wire. The first transmissive electrode is disposed on the substrate and has at least one first electrode. The first wire is disposed on the substrate and connects to the first electrode of the first transmissive electrode. The first receiving electrode is disposed on the substrate and has at least one second electrode. The second wire is disposed on the substrate and extends along a first direction to connect to the first receiving electrode. The first electrode has a plurality of first slits and the second electrode has a plurality of second slits. | 03-27-2014 |
20140132582 | SHIFT REGISTER CIRCUIT - A shift register circuit includes plural stages of shift registers. Each stage of shift register includes a pull-up circuit, a first driving circuit and a voltage-stabilizing circuit. The pull-up circuit is used for charging a first node. The first driving circuit is electrically connected with the first node. According to a voltage level of the first node, a corresponding control signal is outputted from an output terminal of the first driving circuit. The voltage-stabilizing circuit is electrically connected with the output terminal of the first driving circuit for stabilizing the control signal from the first driving circuit. Some circuits of some other shift registers are controlled according to the control signal. | 05-15-2014 |
20140203302 | PIXEL STRUCTURE OF DISPLAY PANEL - A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode. | 07-24-2014 |
Patent application number | Description | Published |
20120248431 | TRANSISTOR ARRAY SUBSTRATE - A transistor array substrate includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units. The scan lines and the data lines are all disposed on the substrate. Each pixel unit includes a transistor and a pixel electrode. The transistor is electrically connected to the pixel electrodes, the scan lines and the data lines. Each transistor includes a gate, a drain, a source, a metal-oxide-semiconductor layer and a channel protective layer. A channel gap exists between the drain and the source. The metal-oxide-semiconductor layer has a pair of side edges opposite to each other and the side edges are located at two ends of the channel gap. The channel protective layer covers the metal-oxide-semiconductor layer in the channel gap and protrudes from the side edges of the metal-oxide-semiconductor layer. | 10-04-2012 |
20130201086 | ACTIVE LIGHT EMITTING DEVICE - An active light emitting device disposed on a substrate is provided. The active light emitting device includes a scan line, a data line, a power line, a circuit unit, and a light emitting unit. The circuit unit is connected to the scan line, the data line, and the power line. The circuit unit at least includes an overlapping component which is at least partially overlapped with the power line. The light emitting unit is driven by the circuit unit. A light emitting region and a circuit region on the substrate are defined respectively by the light emitting unit and the circuit unit. | 08-08-2013 |
20130335394 | DRIVING CIRCUIT OF AN ORGANIC LIGHT EMITTING DEVICE AND METHOD OF OPERATING A DRIVING CIRCUIT OF AN ORGANIC LIGHT EMITTING DEVICE - A driving circuit of an organic light emitting device includes a switch module, a capacitor, and a driving unit. The switch module includes a first switch unit and a second switch unit. The first switch unit is coupled to a data line. The second switch unit is coupled to the organic light emitting device. During a programming period, the first switch unit is turned on and the second switch unit is turned off; and during an emission period, the first switch unit is turned off and the second switch unit is turned on. The capacitor is coupled to the first switch unit for being charged to a data voltage according to a data current of the data line during the programming period. The driving unit is used for generating a driving current to drive the organic light emitting device according to the data voltage during the emission period. | 12-19-2013 |
20150214441 | LIGHT EMITTING DIODE PACKAGE AND ILLUMINATING DEVICE - A LED package including a transparent substrate, at least one LED chip, a first sealing layer and a second sealing layer is provided. The transparent substrate has a first surface and a second surface opposite the first surface. The LED chip is disposed on the first surface of the transparent substrate. The first sealing layer is disposed on the first surface of the transparent substrate and covers the LED chip. The second sealing layer is disposed on the second surface of the transparent substrate and overlaps with the LED chip in a direction perpendicular to the transparent substrate. The LED chip is used to emit a light beam. A portion of the light beam exits the LED package by passing through the transparent substrate and the second sealing layer. Moreover, an illuminating device including the aforementioned LED package is also provided. | 07-30-2015 |