Patent application number | Description | Published |
20120144217 | Dynamically Modifying A Power/Performance Tradeoff Based On Processor Utilization - In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed. | 06-07-2012 |
20120185706 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CONTROL OF ENERGY CONSUMPTION IN POWER DOMAINS - An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit. | 07-19-2012 |
20120204042 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 08-09-2012 |
20130179706 | User Level Control Of Power Management Policies - In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed. | 07-11-2013 |
20130275737 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130275796 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130332753 | DYNAMIC POWER LIMIT SHARING IN A PLATFORM - A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention. | 12-12-2013 |
20140006673 | UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS | 01-02-2014 |
20140006761 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS | 01-02-2014 |
20140129858 | METHOD AND APPARATUS FOR SETTING AN I/O BANDWIDTH-BASED PROCESSOR FREQUENCY FLOOR - An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The | 05-08-2014 |
20140173248 | Performing Frequency Coordination In A Multiprocessor System Based On Response Timing Optimization - In an embodiment, a processor includes a core to execute instructions and a logic to receive memory access requests from the core and to route the memory access requests to a local memory and to route snoop requests corresponding to the memory access requests to a remote processor. The logic is configured to maintain latency information regarding a difference between receipt of responses to the snoop requests from the remote processor and receipt of responses to the memory access requests from the local memory. Other embodiments are described and claimed. | 06-19-2014 |
20140173297 | Performing Frequency Coordination In A Multiprocessor System - In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed. | 06-19-2014 |
20140176581 | CONTROLLING CONFIGURABLE PEAK PERFORMANCE LIMITS OF A PROCESSOR - In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed. | 06-26-2014 |
20140181538 | Controlling Configurable Peak Performance Limits Of A Processor - In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed. | 06-26-2014 |
20140181596 | WEAR-OUT EQUALIZATION TECHNIQUES FOR MULTIPLE FUNCTIONAL UNITS - Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units. | 06-26-2014 |
20140189694 | MANAGING PERFORMANCE POLICIES BASED ON WORKLOAD SCALABILITY - Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles. | 07-03-2014 |
20140195828 | DYNAMICALLY MEASURING POWER CONSUMPTION IN A PROCESSOR - In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed. | 07-10-2014 |
20140281445 | PROCESSOR HAVING FREQUENCY OF OPERATION INFORMATION FOR GUARANTEED OPERATION UNDER HIGH TEMPERATURE EVENTS - A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event. | 09-18-2014 |
20140281612 | MEASUREMENT OF PERFORMANCE SCALABILITY IN A MICROPROCESSOR - A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability. | 09-18-2014 |
20150058650 | Forcing Core Low Power States In A Processor - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed. | 02-26-2015 |
20150067361 | Adaptively Controlling Low Power Mode Operation For A Cache Memory - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed. | 03-05-2015 |
20150089287 | EVENT-TRIGGERED STORAGE OF DATA TO NON-VOLATILE MEMORY - An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system. | 03-26-2015 |