Koju
Toshihiko Koju, Kawasaki-Shi JP
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20110047364 | Recovering from an Error in a Fault Tolerant Computer System - A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed. | 02-24-2011 |
Toshihiko Koju, Kawasaki JP
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20130159678 | Code optimization by memory barrier removal and enclosure within transaction - A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution. | 06-20-2013 |
Toshihiko Koju, Kanagawa JP
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20130198498 | COMPILING METHOD, PROGRAM, AND INFORMATION PROCESSING APPARATUS - A method, program, and apparatus for optimizing compiled code using a dynamic compiler. The method includes the steps of: generating intermediate code from a trace, which is an instruction sequence described in machine language; computing an offset between an address value, which is a base point of an indirect branch instruction, and a start address of a memory page, which includes a virtual address referred to by the information processing apparatus immediately after processing a first instruction; determining whether an indirect branch instruction that is subsequent to the first instruction causes processing to jump to another memory page, by using a value obtained from adding the offset to a displacement made by the indirect branch instruction; and optimizing the intermediate code by using the result of the determining step. | 08-01-2013 |
Toshihiko Koju, Chiba JP
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20140317608 | METHOD FOR OPTIMIZING BINARY CODE IN LANGUAGE HAVING ACCESS TO BINARY CODED DECIMAL VARIABLE, AND COMPUTER AND COMPUTER PROGRAM - A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables. | 10-23-2014 |
Toshihiko Koju, Tokyo JP
Patent application number | Description | Published |
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20150234736 | TESTING OPTIMIZED BINARY MODULES - Various embodiments test an optimized binary module. In one embodiment, a region in a set of original binary code of an original binary module in which branch coverage is expected to be achieved is selected based on a set of profile information. The region is selected as a target region to be optimized. An optimized binary module is created, where the target region has been optimized in the optimized binary module. The optimized binary module is verified by synchronizing execution of the optimized binary module with execution of the original binary module at a checkpoint while executing both the optimized binary module and the original binary module. The optimized binary module is further verified by comparing an output from executing the optimized binary module to an output from executing the original binary module. | 08-20-2015 |