Koji Miyata
Koji Miyata, Ehime JP
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20090282427 | SLOT-IN TYPE DISK APPARATUS - It is an object of the present invention to provide a slot-in type disk apparatus which can be reduced in thickness by precisely guiding a moving position of a disk when the disk is inserted and discharged. The slot-in type disk apparatus in which a base body | 11-12-2009 |
20100223635 | SLOT-IN TYPE DISK APPARATUS - It is an object of the present invention to provide a slot-in type disk apparatus in which a moving position of a disk is precisely guided when the disk is inserted or discharged, thereby preventing the disk from coming into contact with an objective lens and further reducing the thickness of the disk apparatus. In the slot-in type disk apparatus, a base body | 09-02-2010 |
20100223636 | SLOT-IN TYPE DISK APPARATUS - It is an object of the present invention to provide a slot-in type disk apparatus which can be reduced in thickness without deteriorating strength of a lever and a rear base. In a slot-in type disk apparatus, a base body | 09-02-2010 |
20110247025 | DISK CASE AND DETERMINING METHOD THEREOF - It is an object of the invention to provide a disk case capable of easily determining a disk without changing hardware of a drive unit. A disk case of the present invention includes a case body in which a disk is held, an opening through which a portion of the disk is exposed, a shutter for opening and closing the opening, and a bridge portion located at an outer periphery of the disk and at the opening, wherein a dent having a diameter greater than an inner peripheral diameter of the bridge portion is formed at a position of a pickup moving path of the bridge portion. | 10-06-2011 |
Koji Miyata, Osaka-Shi JP
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20100148311 | SEMICONDUCTOR DEVICE - Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs. | 06-17-2010 |
Koji Miyata, Mahopac, NY US
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20100096699 | PREVENTION OF PLASMA INDUCED DAMAGE ARISING FROM ETCHING OF CRACK STOP TRENCHES IN MULTI-LAYERED LOW-K SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench. | 04-22-2010 |
Koji Miyata, Kagoshima JP
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20090243015 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, includes the steps of: forming a resin layer on an upper surface of a substrate including a photodiode such that the resin layer does not cover a light receiving region of the photodiode; forming at least one groove in the resin layer so as to surround the light receiving region; and subsequently mold-sealing the photodiode by loading the substrate into a mold and filling the mold with a molding resin. | 10-01-2009 |
20120161271 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a substrate including a photodiode; a resin layer formed on an upper surface of the substrate, the resin layer not covering a light receiving region of the photodiode, the resin layer including at least one groove surrounding the light receiving region; and a molding resin portion formed by mold-sealing the photodiode with the resin layer thereon so as not to cover the light receiving region. | 06-28-2012 |
Koji Miyata, Yao-Shi JP
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20080237898 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, HEAT SINK, SEMICONDUCTOR CHIP, INTERPOSER SUBSTRATE, AND GLASS PLATE - A semiconductor device of the present invention includes: a laminate structure, including a semiconductor chip, partially sealed with a resin; and a stress relief section for relieving a stress during resin sealing, provided as a convex section including a plain top surface on an uppermost section of the laminate structure, the stress relief section being provided in an annular shape on a peripheral region of the uppermost section so as to come into contact with the sealing resin. This makes it possible to improve the manufacturing yield of the semiconductor device in which the member of the uppermost section is exposed. | 10-02-2008 |
Koji Miyata, Takefu-Shi JP
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20080218298 | Sealed Rare Earth Magnet and Method for Manufacturing the Same - It is an object of the present invention to provide a rare earth magnet that will not decompose due to hydrogen embrittlement when used in a hydrogen gas atmosphere, and furthermore, does not pose the risk of contaminating a reaction bath with the surface treated film of the magnet. The present invention provides a sealed rare earth magnet comprising: a rare earth magnet; and a case of aluminum or aluminum alloy, wherein the case covers entirety of the rare earth magnet and is sealed by HIP; and the methods for manufacturing the same. | 09-11-2008 |
20110192018 | METHOD OF MAKING A MOTOR WITH REDUCED COGGING TORQUE - To reduce the cogging torque of servomotors, electric power steering motors, and others, there is provided a permanent magnet motor comprising: a rotor | 08-11-2011 |
20110232846 | MAGNETIC FIELD GENERATOR FOR MAGNETRON PLASMA - Disclosed is a magnetic field generator for magnetron plasma. The magnetic field generator is provided with a plurality of magnetic segments, and generates a predetermined multi-pole magnetic field around the periphery of a workpiece substrate within a process chamber. The strength of the multi-pole magnetic field is controlled so that the state of the multi-pole magnetic field is matched different plasma processes. Further, the pattern of the multi-pole magnetic field can be changed so as to match different sizes of the substrate. | 09-29-2011 |
Koji Miyata, Kanagawa JP
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20110140065 | MEMORY ELEMENT AND MEMORY DEVICE - The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions. | 06-16-2011 |
20120091428 | MANUFACTURING METHOD OF MEMORY APPARATUS, MEMORY DEVICE AND MEMORY APPARATUS - A manufacturing method of a memory apparatus in which memory devices each having a memory layer whose resistance value reversibly varies by voltage application between bottom and upper electrodes are formed, includes: forming and shaping a bottom electrode material film into a first linear pattern extending in a first direction; forming a memory layer material film and an upper electrode material film in this order on the bottom electrode material film; forming the upper electrodes and the memory layers by shaping the upper electrode material film and the memory layer material film into a second linear pattern extending in a second direction intersecting with the first direction; and forming the bottom electrodes having a quadrangle plane shape at regions where the first linear pattern intersect with the second linear pattern by shaping the bottom electrode material film into the second linear pattern. | 04-19-2012 |
20120127778 | MEMORY DEVICE - A memory device includes: a transistor array having transistors; and memory elements provided, one for each of the transistors. The transistor array includes a substrate having diffusion layers on a surface thereof, parallel word lines on the substrate, parallel first bit lines provided in a direction perpendicular to the word lines, bit contact electrodes between the adjacent two word lines and connecting the first bit lines and the diffusion layers, and node contact electrodes at an opposite side to the bit contact electrodes with the two word lines in between and connected to the diffusion layers. The memory elements have lower electrodes connected to the node contact electrodes, memory layers on the lower electrodes and having resistance values reversibly changing by voltage application, and parallel second bit lines extending in the same direction as that of the first bit lines on the memory layers. | 05-24-2012 |
20150333256 | MEMORY ELEMENT WITH ION CONDUCTOR LAYER IN WHICH METAL IONS DIFFUSE AND MEMORY DEVICE INCORPORATING SAME - The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions. | 11-19-2015 |
Koji Miyata, Fukui JP
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20110210810 | ND BASED SINTERED MAGNET AND ITS PREPARATION - The invention provides a sintered Nd base magnet which is free of a decline of remanence, has a high coercive force, especially at the edges thereof, is unsusceptible to demagnetization even at high temperature, and is suited for use in permanent magnet rotary machines. | 09-01-2011 |
Koji Miyata, Echizen-Shi JP
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20140167895 | METHOD OF MANUFACTURING AN Nd BASED SINTERED MAGNET - A sintered Nd base magnet segment has a coercive force high at the periphery and lower toward the inside. A method for preparing the magnet includes the steps of: (a) providing a sintered Nd base magnet block having surfaces and a magnetization direction, (b) coating the surfaces of the magnet block excluding the surface perpendicular to the magnetization direction with a Dy or Tb oxide powder, a Dy or Tb fluoride powder, or a Dy or Tb-containing alloy powder, (c) treating the coated block at a high temperature for causing Dy or Tb to diffuse into the block, and (d) cutting the block in a plane perpendicular to the magnetization direction into a magnet segment having a coercive force distribution on the cut section that the coercive force is high at the periphery and lower toward the inside and a constant coercive force distribution in the magnetization direction. | 06-19-2014 |
Koji Miyata, Boise, ID US
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20140252471 | Shared contacts for mosfet devices - In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET. | 09-11-2014 |
Koji Miyata, Peachtree City, GA US
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20160104840 | RESISTIVE MEMORY WITH A THERMALLY INSULATING REGION - A resistive memory includes a memory cell having a first electrode, a second electrode and a resistive memory element between the first electrode and the second electrode. The memory cell includes a thermally insulating region. The thermally insulating region may be included in at least one electrode of the memory cell and/or within an electrically insulating region. The thermally insulating region can confine heat within the memory cell and thereby can reduce the current and/or voltage needed to write information in the resistive memory element. | 04-14-2016 |