Patent application number | Description | Published |
20080219341 | Space-frequency equalization for oversampled received signals - Techniques for performing space-frequency equalization and spatial equalization in the frequency domain are described. Space-frequency equalization combines signal components across both space and frequency dimensions whereas spatial equalization combines signal components across space. A receiver obtains input symbols for multiple (M) signal copies from multiple (R) receive antennas and multiple (C) times oversampling, where M is equal to R times C. For space-frequency equalization, the receiver derives equalizer coefficients for the M signal copies, e.g., based on MMSE criterion, filters, the input symbols for the M signal copies with the equalizer coefficients, and combines the filtered symbols for the M signal copies to obtain output symbols. Space-frequency equalization may be used for some frequency bins and spatial equalization may be used for other frequency bins to reduce complexity. | 09-11-2008 |
20080247364 | CYCLIC DELAY DIVERSITY AND PRECODING FOR WIRELESS COMMUNICATION - Techniques for sending a MIMO transmission using a combination of cyclic delay diversity and precoding are described. A set of delays (e.g., zero delay, small delay, and large delay) for cyclic delay diversity and a set of precoding matrices may be supported. In one design, a Node B may select a delay specifically for a UE or for a set of UEs served by the Node B. In another design, a UE may evaluate different combinations of precoding matrix and delay, determine the combination with the best performance, and send this combination of precoding matrix and delay to the Node B. The Node B may perform precoding with the precoding matrix and then processing for cyclic delay diversity based on the selected delay. Alternatively, the Node B may perform processing for cyclic delay diversity based on the selected delay and then precoding with the precoding matrix. | 10-09-2008 |
20090131037 | FAST CELL SEARCH - Systems and methodologies are described that facilitate searches for a cell in a wireless communication environment. A mobile device can employ a searcher that can detect timing information respectively associated with PSCs and cells to determine the cell with the highest correlation. The searcher can detect SSCs, which can include detecting associated phase information, to determine the SSC with the highest correlation, CP length, and/or other information to facilitate identifying a desired cell having the strongest signal to establish communication between the mobile device and the desired cell. PSCs respectively associated with cells can have different positions in the symbol sequences, and SSCs can respectively be phase shifted at different angles to facilitate detection and identification of a cell(s), where a PSC can be utilized as a phase reference by the associated SSC. | 05-21-2009 |
20100310027 | METHOD AND SYSTEM FOR CHANNEL EQUALIZATION - One embodiment includes a method of receiving a transmitted signal. The method comprises receiving a signal transmitted over a channel. The signal comprises a known signal and an information signal. The method further includes determining at least one indicator of channel characteristics based at least in part on the portion of the known signal. The method further includes generating a first value indicative of the information signal based at least in part on the at least one indicator of the channel characteristics. The first value comprises an error signal. The method further comprises removing the error signal from the first estimate of the signal based at least in part on the portion of the known signal. Other embodiments include systems for performing the method and methods of making such systems. | 12-09-2010 |
20110310952 | METHOD AND APPARATUS FOR BLOCK-WISE DECISION-FEEDBACK EQUALIZATION FOR WIRELESS COMMUNICATION - Techniques for performing decision feedback equalization are described. A feed-forward filter response and a feedback filter response are derived based on a channel estimate and a reliability parameter and further without constraint on the feedback filter response or with a constraint of no feedback for an on-time sample. The reliability parameter is indicative of the reliability of the feedback used for equalization and may be frequency dependent or frequency invariant. Different feed-forward and feedback filter responses may be derived with different constraints on the feedback filter and different assumptions for the reliability parameter. Equalization is performed with the feed-forward and feedback filter responses. If equalization is performed for multiple iterations then, for each iteration, the reliability parameter may be updated, the feed-forward and feedback filter responses may be derived based on the updated reliability parameter, and equalization may be performed with the filter responses for the iteration. | 12-22-2011 |
20120020426 | TRANSMIT FORMAT SELECTION WITH CONSIDERATION FOR RESOURCE REUSE - Techniques for selecting transmit formats in a manner to account for the degrees of resource reuse for multiple data streams sent simultaneously from multiple antennas are described. The degree of resource reuse for each data stream indicates the amount of reuse of resources (e.g., orthogonal codes or subcarriers) observed by that stream. Interference estimates for the multiple data streams are derived based on an initial resource assignment. The degrees of resource reuse are determined based on the interference estimates and are used to derive at least one correction factor. At least one transmit format is then selected for the data streams using the at least one correction factor. Each data stream is associated with a transmit format that indicates the amount of resources to use for the data stream and other parameters. Resources are assigned to each data stream in accordance with its transmit format. | 01-26-2012 |
20120122446 | FAST CELL SEARCH - Systems and methodologies are described that facilitate searches for a cell in a wireless communication environment. A mobile device can employ a searcher that can detect timing information respectively associated with PSCs and cells to determine the cell with the highest correlation. The searcher can detect SSCs, which can include detecting associated phase information, to determine the SSC with the highest correlation, CP length, and/or other information to facilitate identifying a desired cell having the strongest signal to establish communication between the mobile device and the desired cell. PSCs respectively associated with cells can have different positions in the symbol sequences, and SSCs can respectively be phase shifted at different angles to facilitate detection and identification of a cell(s), where a PSC can be utilized as a phase reference by the associated SSC. | 05-17-2012 |
20130003816 | METHOD AND APPARATUS FOR CHANNEL AND NOISE ESTIMATION - Techniques for performing channel and noise estimation for a MIMO transmission sent from multiple transmit antennas to multiple receive antennas are described. Samples are obtained from the receive antennas. For a first scheme, channel estimates are derived by correlating the samples with at least one pilot sequence, and signal, noise and interference statistics are also estimated based on the samples. For a second scheme, total received energy as well as signal and interference energy are estimated based on the samples. Noise is then estimated based on the estimated total received energy and the estimated signal and interference energy. For a third scheme, signal and on-time interference statistics are estimated based on the samples. Noise and multipath interference statistics are also estimated based on the samples. Signal, noise and interference statistics are then estimated based on the estimated signal and on-time interference statistics and the estimated noise and multipath interference statistics. | 01-03-2013 |
20140135001 | Fast Cell Search - Systems and methodologies are described that facilitate searches for a cell in a wireless communication environment. A mobile device can employ a searcher that can detect timing information respectively associated with PSCs and cells to determine the cell with the highest correlation. The searcher can detect SSCs, which can include detecting associated phase information, to determine the SSC with the highest correlation, CP length, and/or other information to facilitate identifying a desired cell having the strongest signal to establish communication between the mobile device and the desired cell. PSCs respectively associated with cells can have different positions in the symbol sequences, and SSCs can respectively be phase shifted at different angles to facilitate detection and identification of a cell(s), where a PSC can be utilized as a phase reference by the associated SSC. | 05-15-2014 |
20140205036 | System and Methods for Reducing Uplink Resources to Provide Channel Performance Feedback for Adjustment of Downlink MIMO Channel Data Rates - Systems and methods for improving the performance of a MIMO wireless communication system by reducing the amount of uplink resources that are needed to provide channel performance feedback for the adjustment of data rates on the downlink MIMO channels. In one embodiment, a method comprises encoding each of a set of data streams according to corresponding data rates, permuting the data streams on a set of MIMO channels according to a full permutation of combinations, transmitting the permuted data streams, receiving the permuted data streams, decoding and determining an SNR for each of the data streams, computing a condensed SNR metric for the set of data streams, providing the condensed metric as feedback, determining a set of individual SNR metrics for the data streams based on the condensed SNR metric, and adjusting the data rates at which the data streams are encoded based on the individual SNR metrics. | 07-24-2014 |
Patent application number | Description | Published |
20120242627 | AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR FABRICATION METHOD - This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed. | 09-27-2012 |
20130037793 | AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR FABRICATION METHOD - This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel area of the substrate, and a first metal layer on the dielectric layer. Hydrogen ions are implanted with a plasma-immersion ion implantation process in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The hydrogen ion implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate. | 02-14-2013 |
20130135705 | SYSTEMS, DEVICES, AND METHODS FOR DRIVING AN ANALOG INTERFEROMETRIC MODULATOR - This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for accurately positioning a movable conductive layer of a reflective display element. In one aspect, an initial position of the movable conductive layer with respect to at least one or more fixed conductive layers is sensed. A charging voltage may be determined based at least in part on the initial position. The charging voltage may be applied to the movable conductive layer. | 05-30-2013 |
20130293523 | VOLTAGE BIASED PULL ANALOG INTERFEROMETRIC MODULATOR WITH CHARGE INJECTION CONTROL - This disclosure provides systems, methods and apparatus for driving three-terminal electromechanical systems (EMS) devices. The driving systems and methods described herein include a switched capacitor charge injection circuit that is configured to isolate a single EMS device and transfer a desired amount of charge to the isolated device such that the device can be actuated to produce a desired optical, electrical or mechanical effect. The charge injection circuit can include an operational amplifier and can be connected such that the EMS device is placed in the feedback path of the operational amplifier. | 11-07-2013 |
20140027758 | MULTI-GATE THIN-FILM TRANSISTOR - This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load. | 01-30-2014 |
20140063022 | ELECTROMECHANICAL SYSTEMS DEVICE - This disclosure provides systems, methods and apparatus for electromechanical systems devices including one or more storage capacitors. In one aspect, a device includes a substrate structure, a movable element configured to move relative to the substrate structure, and at least one switch. The movable element includes a first conductive layer and a second conductive layer that form a storage capacitor. The switch is configured to control a flow of charge between a source and the storage capacitor. | 03-06-2014 |
20140210835 | METAL OXIDE LAYER COMPOSITION CONTROL BY ATOMIC LAYER DEPOSITION FOR THIN FILM TRANSISTOR - This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least two metal oxides, with the two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer. The TFT device also includes a source metal adjacent to a portion of the oxide semiconductor layer and a drain metal adjacent to another portion of the oxide semiconductor layer. The composition of the oxide semiconductor layer can be precisely controlled by a sequential deposition technique using atomic layer deposition (ALD). | 07-31-2014 |
20140354655 | REDUCING FLOATING NODE LEAKAGE CURRENT WITH A FEEDBACK TRANSISTOR - This disclosure provides circuits and methods for reducing sub-threshold leakage currents discharging floating nodes. In one aspect, feedback from a floating node is provided to a feedback transistor configured to bias other nodes such that leakage through turned-off transistors is reduced. Additionally, leakage contributing to static power consumption may also be reduced. | 12-04-2014 |
20150070320 | PHOTOCONDUCTIVE OPTICAL TOUCH - An optical touch sensor may include traces of photoconductive material formed on a substantially transparent substrate. Each photoconductive trace may be capable of responding to an incident light intensity increase on a portion of the photoconductive trace by increasing the number of charged carriers, thereby raising the electrical conductivity of that portion of the photoconductive trace. An incident light intensity decrease on a portion of the photoconductive trace will lower the electrical conductivity of that portion of the photoconductive trace. The corresponding changes in voltage may be measured by circuits that include conductive traces formed substantially perpendicular to, and configured for electrical connection with, the traces of photoconductive material. A diode (such as a Schottky diode) may be formed at the electrical connections between the conductive traces and the photoconductive traces. | 03-12-2015 |
20150070747 | DISPLAY ELEMENT RESET USING POLARITY REVERSAL - This disclosure provides circuits and methods for resetting a movable element, such as a mirror of an interferometric modulator (IMOD), to a consistent starting point or reset position. In one example, a circuit may include three electrodes with a capacitor coupled between two of the electrodes. Additionally, the polarity of one of the electrodes may be configured to switch and reverse in polarity relative to another electrode. Accordingly, the movable element may be moved to a reset position. | 03-12-2015 |
Patent application number | Description | Published |
20110170338 | System and Method to Control A Direction of a Current Applied to a Magnetic Tunnel Junction - A system and method to control a direction of a current applied to a magnetic tunnel junction is disclosed. In a particular embodiment, an apparatus comprises a magnetic tunnel junction (MTJ) storage element and a sense amplifier. The sense amplifier is coupled to a first path and to a second path. The first path includes a first current direction selecting transistor and the second path includes a second current direction selecting transistor. The first path is coupled to a bit line of the MTJ storage element and the second path is coupled to a source line of the MTJ storage element. | 07-14-2011 |
20110194333 | System and Method to Select a Reference Cell - A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of the memory in response to a first reference cell in the first bank being indicated as bypassed. | 08-11-2011 |
20110228594 | Multi-Port Non-Volatile Memory that Includes a Resistive Memory Element - A system and method to access a multi-port non-volatile memory that includes a resistive memory element is disclosed. In a particular embodiment, a multi-port non-volatile memory device is disclosed that includes a resistive memory cell and multiple ports coupled to the resistive memory cell. | 09-22-2011 |
20110228595 | Memory Cell That Includes Multiple Non-Volatile Memories - A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element. | 09-22-2011 |
20110235391 | Reference Cell Write Operations At A Memory - A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command. | 09-29-2011 |
20110238203 | Method and Apparatus to Provide a Clock Signal to a Charge Pump - A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to a second charge pump unit of the charge pump. A low-to-high transition of the first clock signal occurs substantially concurrently with a high-to-low transition of the second clock signal. Only one clock signal may be at a logic high voltage level at any given time. | 09-29-2011 |
20110249490 | Asymmetric Write Scheme for Magnetic Bit Cell Elements - Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element. | 10-13-2011 |
20110280057 | Memory Device Having A Local Current Sink - A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line. | 11-17-2011 |
20110280065 | Write Energy Conservation In Memory - A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written. | 11-17-2011 |
20120014174 | Programmable Write Driver For STT-MRAM - A non-volatile memory structure comprises programmable write drivers for controlling drive strengths of write operations to storage elements. The memory structure comprises a storage element coupled to a bit line, a switching element coupled to the storage element, a source line and a word line, wherein the switching element is configured to change a logic state of the storage element. A first and a second write driver with programmable drive strengths are coupled to the bit line and source line respectively to enable control of drive strengths of write operations to the storage element. | 01-19-2012 |
20120026783 | Latching Circuit - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path. | 02-02-2012 |
20120033490 | Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction - A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. | 02-09-2012 |
20120040712 | System and Method to Initiate a Housekeeping Operation at a Mobile Device - A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode. | 02-16-2012 |
20120044755 | System and Method of Reference Cell Testing - In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. | 02-23-2012 |
20120057400 | System and Method for Shared Sensing MRAM - Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array. | 03-08-2012 |
20120075906 | Resistance Based Memory Having Two-Diode Access Device - A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line. | 03-29-2012 |
20120087184 | Magnetic Random Access Memory (MRAM) Layout with Uniform Pattern - A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 04-12-2012 |
20120188816 | Row-Decoder Circuit and Method with Dual Power Systems - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 07-26-2012 |
20120188817 | Read Sensing Circuit and Method with Equalization Timing - A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read operation and to decouple the output node from the reference node after an equalization delay period. A sense amplifier is enabled to provide a data output from the bit cell only after the delay period and decoupling of the output node from the reference node to provide balanced sensing speed of data represented by parallel and antiparallel state magnetic tunnel junctions (MTJs). | 07-26-2012 |
20120218805 | Configurable Memory Array - Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode. | 08-30-2012 |
20120218815 | Magnetic Random Access Memory (MRAM) Read With Reduced Disburb Failure - Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ. | 08-30-2012 |
20120275212 | Self-Body Biasing Sensing Circuit for Resistance-Based Memories - A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage. | 11-01-2012 |
20130003447 | SENSING CIRCUIT - A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit. | 01-03-2013 |
20130028009 | NON-VOLATILE MEMORY SAVING CELL INFORMATION IN A NON-VOLATILE MEMORY ARRAY - Systems and methods for saving repair cell address information in a non-volatile magnetoresistive random access memory (MRAM) having an array of MRAM cells are disclosed. A memory access circuit is coupled to the MRAM, and is configured to store failed cell address information in the MRAM. | 01-31-2013 |
20130039119 | MEMORY CELL THAT INCLUDES MULTIPLE NON-VOLATILE MEMORIES - A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device includes a plurality of memory cells. At least one of the memory cells includes a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element. Each of the first non-volatile memory and the second non-volatile memory is accessible via multiple ports. | 02-14-2013 |
20130076390 | Programmable Logic Sensing in Magnetic Random Access Memory - A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented. | 03-28-2013 |
20130100725 | SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE - A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits. | 04-25-2013 |
20130114336 | THREE PORT MTJ STRUCTURE AND INTEGRATION - A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process. | 05-09-2013 |
20130121066 | CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT - A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit. | 05-16-2013 |
20130163319 | MULTI-PORT NON-VOLATILE MEMORY THAT INCLUDES A RESISTIVE MEMORY ELEMENT - A particular method of accessing a multi-port non-volatile memory device includes executing a first memory operation with respect to a first memory cell while executing a second memory operation with respect to a second memory cell. The first memory operation is via a first port and the second memory operation is via a second port. The first memory cell includes a first non-volatile memory that includes a first resistive memory structure. The second memory cell includes a second non-volatile memory that includes a second resistive memory structure. The first memory cell and the second memory cell are each accessible via the first port and the second port. | 06-27-2013 |
20130176774 | SYSTEM AND METHOD OF REFERENCE CELL TESTING - Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. | 07-11-2013 |
20130182500 | LATCHING CIRCUIT - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit. | 07-18-2013 |
20130194862 | NON-VOLATILE FLIP-FLOP - A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element. | 08-01-2013 |
20130201757 | MULTI-FREE LAYER MTJ AND MULTI-TERMINAL READ CIRCUIT WITH CONCURRENT AND DIFFERENTIAL SENSING - A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer. | 08-08-2013 |
20130235639 | MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN - A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 09-12-2013 |
20130286721 | LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP - A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage. | 10-31-2013 |
20130293286 | TUNABLE REFERENCE CIRCUIT - A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements. | 11-07-2013 |
20130294150 | METHOD AND APPARATUS FOR TESTING A RESISTIVE MEMORY ELEMENT - Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties. | 11-07-2013 |
20130314980 | ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 11-28-2013 |
20140010006 | NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION - A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ. | 01-09-2014 |
20140043924 | CONFIGURABLE MEMORY ARRAY - Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode. | 02-13-2014 |
20140048894 | MTP MTJ DEVICE - Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage. | 02-20-2014 |
20140050019 | MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS - A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures. | 02-20-2014 |
20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 03-06-2014 |
20140063933 | ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS - A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state. | 03-06-2014 |
20140071738 | REFERENCE CELL REPAIR SCHEME - In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node. | 03-13-2014 |
20140071739 | REFERENCE LEVEL ADJUSTMENT SCHEME - A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions (MTJs) in the reference cells can be programmed to a selected magnetic orientation using the shared write driver circuitry. The programmed reference cells can be merged with other programmed reference cells and/or with fixed reference cells to produce a tunable reference level for comparison with MTJ data cells during a read operation. Sharing write driver circuitry between data cells and reference cells allows programming of reference cells without consuming increased area on a chip or macro. | 03-13-2014 |
20140071740 | OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL - A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell. | 03-13-2014 |
20140071741 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 03-13-2014 |
20140108478 | MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR - A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset. | 04-17-2014 |
20140119097 | RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE - A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line. | 05-01-2014 |
20140133216 | SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE - A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits. | 05-15-2014 |
20140140162 | MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION - A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device. | 05-22-2014 |
20140177325 | INTEGRATED MRAM MODULE - Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability. | 06-26-2014 |
20140211551 | MRAM SELF-REPAIR WITH BIST LOGIC - Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array. | 07-31-2014 |
20140215294 | ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS - A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element. | 07-31-2014 |
20140222880 | METHOD AND APPARATUS FOR GENERATING RANDOM NUMBERS USING A PHYSICAL ENTROPY SOURCE - A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue. | 08-07-2014 |
20140231940 | STT-MRAM DESIGN ENHANCED BY SWITCHING CURRENT INDUCED MAGNETIC FIELD - A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current. | 08-21-2014 |
20140269031 | SYSTEM AND METHOD OF SENSING A MEMORY CELL - A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage. | 09-18-2014 |
20140327105 | ELECTROSTATIC DISCHARGE DIODE - A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via. | 11-06-2014 |
20140379978 | REFRESH SCHEME FOR MEMORY CELLS WITH WEAK RETENTION TIME - A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address. | 12-25-2014 |
20150016204 | INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES - A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations. | 01-15-2015 |
20150022264 | SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION - A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line. | 01-22-2015 |
20150036409 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL USING MAGNETIC TUNNEL JUNCTION CELLS - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. | 02-05-2015 |
20150039848 | METHODS AND APPARATUSES FOR IN-SYSTEM FIELD REPAIR AND RECOVERY FROM MEMORY FAILURES - In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold. | 02-05-2015 |
20150063012 | OFFSET CANCELING DUAL STAGE SENSING CIRCUIT - An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit. | 03-05-2015 |
20150067234 | UNIFIED MEMORY CONTROLLER FOR HETEROGENEOUS MEMORY ON A MULTI-CHIP PACKAGE - An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host. | 03-05-2015 |
20150070978 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell. | 03-12-2015 |
20150085594 | METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL - Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information. | 03-26-2015 |
Patent application number | Description | Published |
20120101826 | DECOMPOSITION OF MUSIC SIGNALS USING BASIS FUNCTIONS WITH TIME-EVOLUTION INFORMATION - Decomposition of a multi-source signal using a basis function inventory and a sparse recovery technique is disclosed. | 04-26-2012 |
20120128160 | THREE-DIMENSIONAL SOUND CAPTURING AND REPRODUCING WITH MULTI-MICROPHONES - Systems, methods, apparatus, and machine-readable media for three-dimensional sound recording and reproduction using a multi-microphone setup are described. | 05-24-2012 |
20120128165 | SYSTEMS, METHOD, APPARATUS, AND COMPUTER-READABLE MEDIA FOR DECOMPOSITION OF A MULTICHANNEL MUSIC SIGNAL - Decomposition of a multichannel signal using direction-of-arrival estimation, a basis function inventory, and a sparse recovery technique is disclosed. | 05-24-2012 |
20120128166 | SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR HEAD TRACKING BASED ON RECORDED SOUND SIGNALS - Systems, methods, apparatus, and machine-readable media for detecting head movement based on recorded sound signals are described. | 05-24-2012 |
20120128175 | SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR ORIENTATION-SENSITIVE RECORDING CONTROL - Systems, methods, apparatus, and machine-readable media for orientation-sensitive selection and/or preservation of a recording direction using a multi-microphone setup are described. | 05-24-2012 |
20120294446 | BLIND SOURCE SEPARATION BASED SPATIAL FILTERING - A method for blind source separation based spatial filtering on an electronic device includes obtaining a first source audio signal and a second source audio signal. The method also includes applying a blind source separation filter set to the first source audio signal and to the second source audio signal to produce a spatially filtered first audio signal and a spatially filtered second audio signal. The method further includes playing the spatially filtered first audio signal over a first speaker to produce an acoustic spatially filtered first audio signal and playing the spatially filtered second audio signal over a second speaker to produce an acoustic spatially filtered second audio signal. The acoustic spatially filtered first audio signal and the acoustic spatially filtered second audio signal produce an isolated acoustic first source audio signal at a first position and an isolated acoustic second source audio signal at a second position. | 11-22-2012 |
20130156198 | AUTOMATED USER/SENSOR LOCATION RECOGNITION TO CUSTOMIZE AUDIO PERFORMANCE IN A DISTRIBUTED MULTI-SENSOR ENVIRONMENT - A wireless device is provided that makes use of other nearby audio transducer devices to generate a surround sound effect for a targeted user. To do this, the wireless device first ascertains whether there are any nearby external microphones and/or loudspeaker devices. An internal microphone for the wireless device and any other nearby external microphones may be used to ascertain a location of the desired/targeted user as well as the nearby loudspeaker devices. This information is then used to generate a surround sound effect for the desired/targeted user by having the wireless device steer audio signals to its internal loudspeakers and/or the nearby external loudspeaker devices. | 06-20-2013 |
20130259254 | SYSTEMS, METHODS, AND APPARATUS FOR PRODUCING A DIRECTIONAL SOUND FIELD - A system may be used to drive an array of loudspeakers to produce a sound field that includes a source component, whose energy is concentrated along a first direction relative to the array, and a masking component that is based on an estimated intensity of the source component in a second direction that is different from the first direction. | 10-03-2013 |
20130272097 | SYSTEMS, METHODS, AND APPARATUS FOR ESTIMATING DIRECTION OF ARRIVAL - Systems, methods, and apparatus for matching pair-wise differences (e.g., phase delay measurements) to an inventory of source direction candidates, and application of pair-wise source direction estimates, are described. | 10-17-2013 |
20130272538 | SYSTEMS, METHODS, AND APPARATUS FOR INDICATING DIRECTION OF ARRIVAL - Systems, methods, and apparatus for projecting an estimated direction of arrival of sound onto a plane that does not include the estimated direction are described. | 10-17-2013 |
20130272539 | SYSTEMS, METHODS, AND APPARATUS FOR SPATIALLY DIRECTIVE FILTERING - Systems, methods, and apparatus are described for applying, based on angles of arrival of source components relative to the axes of different microphone pairs, a spatially directive filter to a multichannel audio signal to produce an output signal. | 10-17-2013 |
20130272548 | OBJECT RECOGNITION USING MULTI-MODAL MATCHING SCHEME - Methods, systems and articles of manufacture for recognizing and locating one or more objects in a scene are disclosed. An image and/or video of the scene are captured. Using audio recorded at the scene, an object search of the captured scene is narrowed down. For example, the direction of arrival (DOA) of a sound can be determined and used to limit the search area in a captured image/video. In another example, keypoint signatures may be selected based on types of sounds identified in the recorded audio. A keypoint signature corresponds to a particular object that the system is configured to recognize. Objects in the scene may then be recognized using a shift invariant feature transform (SIFT) analysis comparing keypoints identified in the captured scene to the selected keypoint signatures. | 10-17-2013 |
20130275077 | SYSTEMS AND METHODS FOR MAPPING A SOURCE LOCATION - A method for mapping a source location by an electronic device is described. The method includes obtaining sensor data. The method also includes mapping a source location to electronic device coordinates based on the sensor data. The method further includes mapping the source location from electronic device coordinates to physical coordinates. The method additionally includes performing an operation based on a mapping. | 10-17-2013 |
20130275872 | SYSTEMS AND METHODS FOR DISPLAYING A USER INTERFACE - A method for displaying a user interface on an electronic device is described. The method includes presenting a user interface. The user interface includes a coordinate system. The coordinate system corresponds to physical coordinates based on sensor data. The method also includes providing a sector selection feature that allows selection of at least one sector of the coordinate system. The method further includes providing a sector editing feature that allows editing the at least one sector. | 10-17-2013 |
20130275873 | SYSTEMS AND METHODS FOR DISPLAYING A USER INTERFACE - A method for displaying a user interface on an electronic device is described. The method includes presenting a user interface. The user interface includes a coordinate system. The coordinate system corresponds to physical coordinates based on sensor data. The method also includes displaying at least a target audio signal and an interfering audio signal on the user interface. | 10-17-2013 |
20130282369 | SYSTEMS AND METHODS FOR AUDIO SIGNAL PROCESSING - A method for signal level matching by an electronic device is described. The method includes capturing a plurality of audio signals from a plurality of microphones. The method also includes determining a difference signal based on an inter-microphone subtraction. The difference signal includes multiple harmonics. The method also includes determining whether a harmonicity of the difference signal exceeds a harmonicity threshold. The method also includes preserving the harmonics to determine an envelope. The method further applies the envelope to a noise-suppressed signal. | 10-24-2013 |
20130282372 | SYSTEMS AND METHODS FOR AUDIO SIGNAL PROCESSING - A method for detecting voice activity by an electronic device is described. The method includes detecting near end speech based on a near end voiced speech detector and at least one single channel voice activity detector. The near end voiced speech detector is associated with a harmonic statistic based on a speech pitch histogram. | 10-24-2013 |
20130282373 | SYSTEMS AND METHODS FOR AUDIO SIGNAL PROCESSING - A method for restoring a processed speech signal by an electronic device is described. The method includes obtaining at least one audio signal. The method also includes performing bin-wise voice activity detection based on the at least one audio signal. The method further includes restoring the processed speech signal based on the bin-wise voice activity detection. | 10-24-2013 |
20130301837 | Audio User Interaction Recognition and Context Refinement - A system which tracks a social interaction between a plurality of participants, includes a fixed beamformer that is adapted to output a first spatially filtered output and configured to receive a plurality of second spatially filtered outputs from a plurality of steerable beamformers. Each steerable beamformer outputs a respective one of the second spatially filtered outputs associated with a different one of the participants. The system also includes a processor capable of determining a similarity between the first spatially filtered output and each of the second spatially filtered outputs. The processor determines the social interaction between the participants based on the similarity between the first spatially filtered output and each of the second spatially filtered outputs. | 11-14-2013 |
20130304476 | Audio User Interaction Recognition and Context Refinement - A system which performs social interaction analysis for a plurality of participants includes a processor. The processor is configured to determine a similarity between a first spatially filtered output and each of a plurality of second spatially filtered outputs. The processor is configured to determine the social interaction between the participants based on the similarities between the first spatially filtered output and each of the second spatially filtered outputs and display an output that is representative of the social interaction between the participants. The first spatially filtered output is received from a fixed microphone array, and the second spatially filtered outputs are received from a plurality of steerable microphone arrays each corresponding to a different participant. | 11-14-2013 |
20130315402 | THREE-DIMENSIONAL SOUND COMPRESSION AND OVER-THE-AIR TRANSMISSION DURING A CALL - A method for encoding multiple directional audio signals using an integrated codec by a wireless communication device is disclosed. The wireless communication device records a plurality of directional audio signals. The wireless communication device also generates a plurality of audio signal packets based on the plurality of directional audio signals. At least one of the audio signal packets includes an averaged signal. The wireless communication device further transmits the plurality of audio signal packets. | 11-28-2013 |
20130317830 | THREE-DIMENSIONAL SOUND COMPRESSION AND OVER-THE-AIR TRANSMISSION DURING A CALL - A method for encoding three dimensional audio by a wireless communication device is disclosed. The wireless communication device detects an indication of a plurality of localizable audio sources. The wireless communication device also records a plurality of audio signals associated with the plurality of localizable audio sources. The wireless communication device also encodes the plurality of audio signals. | 11-28-2013 |
20130339011 | SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR PITCH TRAJECTORY ANALYSIS - Systems, methods, and apparatus for pitch trajectory analysis are described. Such techniques may be used to remove vocals and/or vibrato from an audio mixture signal. For example, such a technique may be used to pre-process the signal before an operation to decompose the mixture signal into individual instrument components. | 12-19-2013 |
20140003611 | SYSTEMS AND METHODS FOR SURROUND SOUND ECHO REDUCTION | 01-02-2014 |
20140003635 | AUDIO SIGNAL PROCESSING DEVICE CALIBRATION | 01-02-2014 |
20140146970 | COLLABORATIVE SOUND SYSTEM - In general, techniques are described for forming a collaborative sound system. A headend device comprising one or more processors may perform the techniques. The processors may be configured to identify mobile devices that each includes a speaker and that are available to participate in a collaborative surround sound system. The processors may configure the collaborative surround sound system to utilize the speaker of each of the mobile devices as one or more virtual speakers of this system and then render audio signals from an audio source such that when the audio signals are played by the speakers of the mobile devices the audio playback of the audio signals appears to originate from the one or more virtual speakers of the collaborative surround sound system. The processors may then transmit the processed audio signals rendered to the mobile device participating in the collaborative surround sound system. | 05-29-2014 |
20140146983 | IMAGE GENERATION FOR COLLABORATIVE SOUND SYSTEMS - In general, techniques are described for image generation for a collaborative sound system. A headend device comprising a processor may perform these techniques. The processor may be configured to determine a location of a mobile device participating in a collaborative surround sound system as a speaker of a plurality of speakers of the collaborative surround sound system. The processor may further be configured to generate an image that depicts the location of the mobile device that is participating in the collaborative surround sound system relative to the plurality of other speakers of the collaborative surround sound system. | 05-29-2014 |
20140146984 | CONSTRAINED DYNAMIC AMPLITUDE PANNING IN COLLABORATIVE SOUND SYSTEMS - In general, techniques are described for performing constrained dynamic amplitude panning in collaborative sound systems. A headend device comprising one or more processors may perform the techniques. The processors may be configured to identify, for a mobile device participating in a collaborative surround sound system, a specified location of a virtual speaker of the collaborative surround sound system and determine a constraint that impacts playback of audio signals rendered from an audio source by the mobile device. The processors may be further configure to perform dynamic spatial rendering of the audio source with the determined constraint to render audio signals that reduces the impact of the determined constraint during playback of the audio signals by the mobile device. | 05-29-2014 |
20140233725 | PERSONALIZED BANDWIDTH EXTENSION - A personalized (i.e., speaker-derivable) bandwidth extension is provided in which the model used for bandwidth extension is personalized (e.g., tailored) to each specific user. A training phase is performed to generate a bandwidth extension model that is personalized to a user. The model may be subsequently used in a bandwidth extension phase during a phone call involving the user. The bandwidth extension phase, using the personalized bandwidth extension model, will be activated when a higher band (e.g., wideband) is not available and the call is taking place on a lower band (e.g., narrowband). | 08-21-2014 |
20140254816 | CONTENT BASED NOISE SUPPRESSION - Apparatus and methods for audio noise attenuation are disclosed. An audio signal analyzer can determine whether an input audio signal received from a microphone device includes a noise signal having identifiable content. If there is a noise signal having identifiable content, a content source is accessed to obtain a copy of the noise signal. An audio canceller can generate a processed audio signal, having an attenuated noise signal, based on comparing the copy of the noise signal to the input audio signal. Additionally or alternatively, data may be communicated on a communication channel to a separate media device to receive at least a portion of the copy of the noise signal from the separate media device, or to receive content-identification data corresponding to the content source. | 09-11-2014 |
20140328490 | MULTI-CHANNEL ECHO CANCELLATION AND NOISE SUPPRESSION - A method for multi-channel echo cancellation and noise suppression is described. One of multiple echo estimates is selected for non-linear echo cancellation. Echo notch masking is performed on a noise-suppressed signal based on an echo direction of arrival (DOA) to produce an echo-suppressed signal. Non-linear echo cancellation is performed on the echo-suppressed signal based, at least in part, on the selected echo estimate. | 11-06-2014 |
20140337021 | SYSTEMS AND METHODS FOR NOISE CHARACTERISTIC DEPENDENT SPEECH ENHANCEMENT - A method for noise characteristic dependent speech enhancement by an electronic device is described. The method includes determining a noise characteristic of input audio. Determining a noise characteristic of input audio includes determining whether noise is stationary noise and determining whether the noise is music noise. The method also includes determining a noise reference based on the noise characteristic. Determining the noise reference includes excluding a spatial noise reference from the noise reference when the noise is stationary noise and including the spatial noise reference in the noise reference when the noise is not music noise and is not stationary noise. The method further includes performing noise suppression based on the noise characteristic. | 11-13-2014 |
Patent application number | Description | Published |
20110280065 | Write Energy Conservation In Memory - A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written. | 11-17-2011 |
20130028009 | NON-VOLATILE MEMORY SAVING CELL INFORMATION IN A NON-VOLATILE MEMORY ARRAY - Systems and methods for saving repair cell address information in a non-volatile magnetoresistive random access memory (MRAM) having an array of MRAM cells are disclosed. A memory access circuit is coupled to the MRAM, and is configured to store failed cell address information in the MRAM. | 01-31-2013 |
20130100725 | SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE - A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits. | 04-25-2013 |
20130114336 | THREE PORT MTJ STRUCTURE AND INTEGRATION - A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process. | 05-09-2013 |
20130176774 | SYSTEM AND METHOD OF REFERENCE CELL TESTING - Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. | 07-11-2013 |
20130235639 | MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN - A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 09-12-2013 |
20130293286 | TUNABLE REFERENCE CIRCUIT - A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements. | 11-07-2013 |
20130294150 | METHOD AND APPARATUS FOR TESTING A RESISTIVE MEMORY ELEMENT - Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties. | 11-07-2013 |
20130314980 | ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 11-28-2013 |
20140010006 | NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION - A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ. | 01-09-2014 |
20140048894 | MTP MTJ DEVICE - Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage. | 02-20-2014 |
20140050019 | MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS - A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures. | 02-20-2014 |
20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 03-06-2014 |
20140071738 | REFERENCE CELL REPAIR SCHEME - In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node. | 03-13-2014 |
20140071739 | REFERENCE LEVEL ADJUSTMENT SCHEME - A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions (MTJs) in the reference cells can be programmed to a selected magnetic orientation using the shared write driver circuitry. The programmed reference cells can be merged with other programmed reference cells and/or with fixed reference cells to produce a tunable reference level for comparison with MTJ data cells during a read operation. Sharing write driver circuitry between data cells and reference cells allows programming of reference cells without consuming increased area on a chip or macro. | 03-13-2014 |
20140071740 | OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL - A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell. | 03-13-2014 |
20140071741 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 03-13-2014 |
20140108478 | MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR - A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset. | 04-17-2014 |
20140119097 | RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE - A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line. | 05-01-2014 |
20140133216 | SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE - A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits. | 05-15-2014 |
20140140162 | MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION - A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device. | 05-22-2014 |
20140211551 | MRAM SELF-REPAIR WITH BIST LOGIC - Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array. | 07-31-2014 |
20140215294 | ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS - A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element. | 07-31-2014 |
20140327105 | ELECTROSTATIC DISCHARGE DIODE - A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via. | 11-06-2014 |
20150022264 | SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION - A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line. | 01-22-2015 |
20150070978 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell. | 03-12-2015 |