Kim, Icheon-Si Gyeonggi-Do
Bo Kyeom Kim, Icheon-Si Gyeonggi-Do KR
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20160086667 | SYSTEM HAVING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels. | 03-24-2016 |
Byung Ryul Kim, Icheon-Si Gyeonggi-Do KR
Chang Geun Kim, Icheon-Si Gyeonggi-Do KR
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20140157082 | DATA STORAGE DEVICE AND METHOD FOR PROCESSING ERROR CORRECTION CODE THEREOF - A data storage device includes a data storage medium, and an error correction code unit configured to process an error correction code for data to be stored in the data storage medium. The error correction code unit includes a storage block configured to store the data to be stored in the data storage medium, and an encoder configured to divide the data stored in the storage block into a plurality of data groups according to an address of the storage block, to encode the plurality of data groups, to encode a plurality of parity data groups that are generated by encoding the plurality of data groups, and to generate final parity data. | 06-05-2014 |
Chang Hyun Kim, Icheon-Si Gyeonggi-Do KR
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20150091612 | NOISE ELIMINATION CIRCUIT OF SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a pulse generation unit configured to detect a transition of an input signal and generate a preliminary pulse signal, and an error elimination unit configured to determine error of the preliminary pulse signal and output a signal as a pulse signal. | 04-02-2015 |
20150302909 | SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD OF THE SAME - A semiconductor memory apparatus includes a delay control portion configured to generate a plurality of control signals by performing subtraction operation on a CL information and an AL information; and a delay portion configured to decide a delay amount, delay an input signal by the delay amount, and output the delayed input signal as a delay signal in response to the plurality of control signals. | 10-22-2015 |
20160071570 | REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor apparatus may include a plurality of slices electrically coupled through through electrodes. Any one slice of the plurality of slices may be configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through electrodes. The other slices may be configured to perform refresh operations in synchronization with the refresh cycle signal. | 03-10-2016 |
Cheol Hoe Kim, Icheon-Si Gyeonggi-Do KR
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20150228311 | SEMICONDUCTOR MEMORY APPARATUS, AND REFERENCE VOLTAGE CONTROL CIRCUIT AND INTERNAL VOLTAGE GENERATION CIRCUIT THEREFOR - An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage. | 08-13-2015 |
20150364164 | PRECHARGE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A semiconductor apparatus includes a memory region configured to store data transmitted through a first data line and a second data line; and a precharge block configured to precharge the second data line to a level of a first voltage and precharge the first data line to a level of a second voltage higher than the level of the first voltage, based on a write signal. | 12-17-2015 |
Chul Kim, Icheon-Si Gyeonggi-Do KR
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20140333271 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first structural body including a first temperature voltage generation unit configured to generate first and second temperature voltages which have different voltage level variations according to a temperature variation, in response to a temperature measurement command, and a first temperature information determination unit configured to generate first temperature information depending on a difference between levels of the first and second temperature voltages; and a second structural body including a second temperature voltage generation unit configured to generate a third temperature voltage and a fourth temperature voltage which have different voltage level variations according to a temperature variation, when a predetermined time elapses after the first and second temperature voltages are generated from the first structural body, and a second temperature information determination unit configured to generate second temperature information depending on a difference between levels of the third and fourth temperature voltages. | 11-13-2014 |
20140357074 | SEMICONDUCTOR APPARATUS AND METHOD OF FABRICATING THE SAME - In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip. | 12-04-2014 |
Dae Suk Kim, Icheon-Si Gyeonggi-Do KR
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20150092484 | SEMICONDUCTOR INTEGRATED CIRCUIT - A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set. | 04-02-2015 |
Dong Hwee Kim, Icheon-Si Gyeonggi-Do KR
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20150117079 | SUB WORD LINE DRIVER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other. | 04-30-2015 |
Dong Keun Kim, Icheon-Si Gyeonggi-Do KR
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20160042770 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first memory cell electrically coupled to a word line and a bit line; a second memory cell electrically coupled to the word line and a bit line bar; a sense amplifier electrically coupled to the bit line and the bit line bar; and a switching unit configured to electrically couple the bit line and the bit line bar to an input/output line and an input/output line bar in response to a column select signal. | 02-11-2016 |
Eun Jun Kim, Icheon-Si Gyeonggi-Do KR
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20130147995 | SIGNAL PROVIDING APPARATUS, AND ANALOG-TO-DIGITAL CONVERTING APPARATUS AND IMAGE SENSOR USING THE SAME - An image sensor includes: a plurality of image pixels providing a reset signal and a data signal; a signal providing apparatus generating a ramp signal, and sequentially providing the reset signal, the data signal, and the ramp signal; and an analog-to-digital converting apparatus converting the data signal into a digital signal by using a first timing at which the amplitude of the ramp signal is changed based on the amplitude of the reset signal and a second timing at which the amplitude of the ramp signal is changed based on the amplitude of the data signal, wherein the reset signal used to generate the ramp signal and the data signal which has been converted into the data digital signal may be output from the same image pixel. | 06-13-2013 |
20130256511 | IMAGE SENSOR - An image sensor includes, inter alia: a first and second capacitors arranged serially between an input terminal and a first node, a first comparing unit connecting to a first reference signal and a connecting node of the first and second capacitors, and an output terminal connecting to the first node wherein the first comparing unit provides first or second preliminary ramp signals on the first node, first and second switches arranged between the first comparing unit and the first capacitor to selectively connect the first capacitor to a ground voltage or the input terminal, a third capacitor connecting to the second capacitor in parallel, a third switch selectively connecting the first node to the third capacitor, a first ramp signal output unit generating a first ramp signal with the first preliminary ramp signal provided, and a second ramp signal output unit generating a second ramp signal using the second preliminary ramp signal. | 10-03-2013 |
Hong Gyeom Kim, Icheon-Si Gyeonggi-Do KR
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20150115435 | SEMICONDUCTOR APPARATUS INCLUDING THROUGH VIA - A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via. | 04-30-2015 |
Hong Jung Kim, Icheon-Si Gyeonggi-Do KR
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20160027491 | REFRESH CIRCUIT - A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period. | 01-28-2016 |
Hyun Sik Kim, Icheon-Si Gyeonggi-Do KR
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20140159792 | VOLTAGE GENERATION CIRCUIT - A voltage generation circuit includes an oscillator configured to output a first period signal and a second period signal in response to a detection signal; a period signal select unit configured to receive the first and second period signals and output one of the first and second period signals as an additional period signal in response to a control signal; and a charge pump unit configured to charge-pump an input voltage in response to the first period signal and the additional period signal and generate a power supply voltage. | 06-12-2014 |
Jong Sam Kim, Icheon-Si Gyeonggi-Do KR
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20150185745 | SEMICONDUCTOR APPARATUS - A voltage generation circuit of a semiconductor apparatus includes a first detection block configured to detect an output voltage and output a first detection signal; a second detection block configured to detect the output voltage and output a second detection signal; a signal generation block configured to generate a control signal in response to the first detection signal and the second detection signal; and a voltage generation block configured to generate the output voltage in response to the control signal, wherein responding speeds of the first detection block and the second detection block with respect to a variation in the output voltage are different. | 07-02-2015 |
20160091911 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code. | 03-31-2016 |
Jong Su Kim, Icheon-Si Gyeonggi-Do KR
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20140320156 | APPARATUS FOR DETECTING MISALIGNMENT OF TEST PAD - An apparatus for detecting misalignment of a test pad and a probe card includes: a test pad unit; a guard unit configured to surround the test pad unit, and formed to maintain a predetermined interval with the test pad unit; and a power supply unit configured to supply a predetermined voltage to the guard unit. | 10-30-2014 |
20140321017 | Semiconductor Integrated Circuit - A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included. | 10-30-2014 |
20160006419 | ELECTRONIC SYSTEMS - An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal. | 01-07-2016 |
20160118375 | SEMICONDUCTOR INTEGRATED CIRCUIT - A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included. | 04-28-2016 |
20160118376 | SEMICONDUCTOR INTEGRATED CIRCUIT - A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included. | 04-28-2016 |
Ju Young Kim, Icheon-Si Gyeonggi-Do KR
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20150092509 | SEMICONDUCTOR APPARATUS AND CHIP ID GENERATION METHOD THEREOF - Provided is a semiconductor apparatus including a plurality of memory chips which are sequentially stacked. Each of the memory chips includes: a temperature sensor configured to sense the temperature of the memory chip; and a chip ID output unit configured to generate a chip ID for the memory chip based on an output of the temperature sensor. | 04-02-2015 |
Keun Hyung Kim, Icheon-Si Gyeonggi-Do KR
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20120213022 | SIP SEMICONDUCTOR SYSTEM - A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system. | 08-23-2012 |
Ki Tae Kim, Icheon-Si Gyeonggi-Do KR
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20160069956 | CHANNEL CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock to buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal. | 03-10-2016 |
Ki Up Kim, Icheon-Si Gyeonggi-Do KR
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20140159765 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: an output timing test unit configured to edge-trigger a pad output data applied from an input/output pad at a first timing and output the edge-triggered pad output data as output timing test data, during an output timing test mode, and a test output unit configured to receive the output timing test data and output the received output timing test data to a probe pad. | 06-12-2014 |
20150095522 | SEMICONDUCTOR MEMORY - A semiconductor memory in accordance with an embodiment includes: a control unit configured to generate a plurality of second control signals in response to a page size signal and a plurality of first control signals; a plurality of input/output switches configured to be coupled to each of a plurality of unit memory blocks and activated in response to the plurality of second control signals; and a plurality of page change switches configured to couple data lines of the plurality of unit memory blocks in response to the page size signal. | 04-02-2015 |
Kwan Dong Kim, Icheon-Si Gyeonggi-Do KR
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20140176207 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal. | 06-26-2014 |
20140361818 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal. | 12-11-2014 |
20150236706 | DELAY LOCKED LOOP AND SEMICONDUCTOR APPARATUS - A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code. | 08-20-2015 |
Kwang Hyun Kim, Icheon-Si Gyeonggi-Do KR
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20150067315 | MEMORY APPARATUS AND COMPUTER SYSTEM INCLUDING THE SAME - A semiconductor device includes a memory bank, a data line and a data line control unit. The memory bank stores data. The data line transfers data to be stored in or output from the memory bank. The data line control unit initializes the data line in response to a power-up signal and a write command. | 03-05-2015 |
Kyung Whan Kim, Icheon-Si Gyeonggi-Do KR
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20150092484 | SEMICONDUCTOR INTEGRATED CIRCUIT - A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set. | 04-02-2015 |
Min Chang Kim, Icheon-Si Gyeonggi-Do KR
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20150043291 | METHOD FOR TESTING SEMICONDUCTOR APPARATUS AND TEST SYSTEM USING THE SAME - This technique may include a semiconductor apparatus configured to perform data read/write operations in a test mode or a normal mode and a tester configured to simultaneously perform a data test and a leakage current test through a write operation using data read by a read operation in the normal mode after writing data into the semiconductor apparatus in the test mode. | 02-12-2015 |
20150155019 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a data latch unit configured to latch arranged data according to a domain crossing control signal, and to output the arranged data as write data; and a domain crossing controller configured to generate the domain crossing control signal with respect to the timing of a data strobe signal. | 06-04-2015 |
Min Su Kim, Icheon-Si Gyeonggi-Do KR
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20160071620 | SEMICONDUCTOR MEMORY APPARATUS AND DATA PROCESSING SYSTEM WITH MAIN MEMORY BLOCKS AND REDUNDANT MEMORY BLOCKS SHARING A COMMON GLOBAL DATA LINE - A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled. | 03-10-2016 |
Myoung Seob Kim, Icheon-Si Gyeonggi-Do KR
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20160118337 | EMBEDDED PACKAGES, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - An embedded package includes a chip having a top surface on which a connection member is disposed, a first insulation layer surrounding a portion of the chip, a second insulation layer disposed on the first insulation layer to cover the chip, circuit patterns disposed on a bottom surface of the first insulation layer, a third insulation layer disposed on the bottom surface of the first insulation layer to cover the circuit patterns, an external connection terminal penetrating the third insulation layer to contact any one of the circuit patterns, a metal layer disposed on a top surface of the second insulation layer, a first via penetrating the first insulation layer to electrically couple the connection member to any one of the circuit patterns, and a second via penetrating the first and second insulation layers to electrically couple the metal layer to any one of the circuit patterns. | 04-28-2016 |
Tae Gyun Kim, Icheon-Si Gyeonggi-Do KR
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20150221389 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. The semiconductor memory device may also include a peripheral circuit suitable for providing a plurality of operation voltages including an erase verify voltage to the plurality of strings, and a control logic suitable for controlling the peripheral circuit to adjust a voltage level of the erase verify voltage applied to a selected memory cell, from among the plurality of drain side memory cells and the plurality of source side memory cells, according to a distance between the selected memory cell and the pipe transistor when an erase verify operation is performed. | 08-06-2015 |
Yeon Uk Kim, Icheon-Si Gyeonggi-Do KR
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20150153794 | SYSTEM INCLUDING MEMORY CONTROLLER FOR MANAGING POWER OF MEMORY - A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device. | 06-04-2015 |
Yong Ju Kim, Icheon-Si Gyeonggi-Do KR
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20150054558 | PHASE MIXING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals. | 02-26-2015 |