Patent application number | Description | Published |
20120029611 | Stent Graft System and Method of Use - A stent graft system and method of use including a stent graft system with a first stent graft component and a second stent graft component. A first tubular graft of the first stent graft component has an integral first body and first leg, with the first body defining a first crown opening and a first substantially elliptical opening. The second body of the second stent graft component is disposed in the first body of the first stent graft component with the second leg of the second stent graft component disposed through the first substantially elliptical opening of the first stent graft component with the perimeter of the first elliptical opening of the first stent graft component in contact with the second body of the second stent graft component. | 02-02-2012 |
20120271399 | High Metal to Vessel Ratio Landing Zone Stent-Graft and Method - A method includes covering an ostium of a branch vessel emanating from a main vessel with a proximal landing zone of a high metal to vessel ratio landing zone stent-graft, wherein a metal to vessel ratio of the proximal landing zone when deployed is sufficiently high to encourage tissue ingrowth around the proximal landing zone yet is sufficiently low to ensure perfusion of the branch vessel through the proximal landing zone. The method further includes covering an aneurysm of the main vessel with an exclusion zone of the high metal to vessel ratio landing zone stent-graft, the exclusion zone being formed of graft material. By forming the exclusion zone of graft material, excellent exclusion of the aneurysm is achieved. | 10-25-2012 |
20130261727 | VARIABLE ZONE HIGH METAL TO VESSEL RATIO STENT AND METHOD - A variable zone high metal to vessel ratio stent includes a proximal high metal to vessel ratio zone, a central low metal to vessel ratio zone, and a distal high metal to vessel ratio zone. The proximal high metal to vessel ratio zone is deployed with fixation and sealing to healthy tissue of a main vessel superior to branch vessels and an aneurysm. The central low metal to vessel ratio zone is deployed directly on ostai of the branch vessels. However, as the central low metal to vessel ratio zone is highly permeable, blood flows from the main vessel through the central low metal to vessel ratio zone and into branch vessels. | 10-03-2013 |
20130261728 | HIGH METAL TO VESSEL RATIO STENT AND METHOD - A method includes covering ostai of branch vessels emanating from a main vessel and an aneurysm with a high metal to vessel ratio stent. A metal to vessel ratio of the high metal to vessel ratio stent is sufficiently high to encourage tissue ingrowth around the high metal to vessel ratio stent yet is sufficiently low to ensure perfusion of the branch vessels through the high metal to vessel ratio stent. The ingrowth of tissue provides secure fixation and sealing of the high metal to vessel ratio stent to the main vessel and remodels and essentially eliminates the aneurysm. Further, as the entire high metal to vessel ratio stent is permeably, the high metal to vessel ratio stent is deployed without having to rotationally position the high metal to vessel ratio stent. | 10-03-2013 |
20130261732 | INTEGRATED MESH HIGH METAL TO VESSEL RATIO STENT AND METHOD - A method includes covering ostai of branch vessels emanating from a main vessel and an aneurysm with an integrated mesh high metal to vessel ratio stent. The integrated mesh high metal to vessel ratio stent includes serpentine rings integrated with an integrated mesh having holes formed therein. A metal to vessel ratio of the integrated mesh high metal to vessel ratio stent is sufficiently high to encourage tissue ingrowth around the integrated mesh high metal to vessel ratio stent yet is sufficiently low to ensure perfusion of the branch vessels through the integrated mesh high metal to vessel ratio stent. | 10-03-2013 |
Patent application number | Description | Published |
20090036592 | POLYMERIC COMPOSITION FOR SEALS AND GASKETS - The present invention relates to a polymeric composition which has an excellent combination of properties for use in making seals and gaskets for utilization in appliances, automotive applications, and building applications, such as window glazing gaskets. These polymeric compositions offer excellent dimensional stability, low compression set, outstanding sealing characteristics, low temperature flexibility, heat resistance and ultra-violet light resistance. The present invention more specifically discloses a polymeric composition having excellent characteristics for utilization in manufacturing seals and gaskets including dimensional stability, low compression set and outstanding sealing characteristics, said polymeric composition being comprised of a blend of (A) a thermoplastic resin selected from the group consisting of polypropylene, polyethylene, poly phenylene ether polystyrene, and styrene containing copolymer resins, (B) an elastomeric polymer selected from the group consisting of block copolymer comprising a first polymeric block that is comprised of repeat units that are derived from a vinyl aromatic monomer and a second block that is comprised of repeat units that are derived from a conjugated diolefin monomer, wherein the repeat units in the second block are hydrogenated, and wherein the repeat units in the second block are elastomeric in nature, and a crosslinked olefinic elastomer, (C) a high molecular weight crosslinked diene elastomer comprised of repeat units that are derived from conjugated diene monomer selected from the group consisting of 1,3-butadiene and isoprene, wherein the high molecular weight diene elastomer has a weight average molecular weight of at least about 200,000, and (D) an oil. | 02-05-2009 |
Patent application number | Description | Published |
20080313494 | MEMORY REFRESH SYSTEM AND METHOD - A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors. | 12-18-2008 |
20090079055 | METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP PACKAGE - Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP. | 03-26-2009 |
20090080279 | STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP - Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage. | 03-26-2009 |
20090113078 | METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed. | 04-30-2009 |
20090113158 | METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew. | 04-30-2009 |
20090129186 | SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS - The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory. | 05-21-2009 |
20090200652 | METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE - A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip. | 08-13-2009 |
20130082718 | CIRCUIT TEST INTERFACE AND TEST METHOD THEREOF - A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad. | 04-04-2013 |
20130141124 | TEST METHOD OF DRIVING APPARATUS AND CIRCUIT TESTING INTERFACE THEREOF - A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad. | 06-06-2013 |