Patent application number | Description | Published |
20080204114 | TRANSMISSION GATE SWITCH, SYSTEM USING THE SAME, AND DATA INPUT/OUTPUT METHOD THEREOF - A transmission gate switch includes a switching unit to conduct a switching operation between first and second nodes in response to a switching signal, and an isolation unit to prevent the switching unit from being turned on by a negative swing of the first or second node while the switching unit is being turned off. | 08-28-2008 |
20090095955 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF - A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal. | 04-16-2009 |
20090113546 | MEMORY SYSTEM FOR SENSING ATTACK - A memory system includes a main memory, a sub-memory, a controller, first and second data readers and a comparator. The main memory stores data and the sub-memory stores data extracted from the data stored in the main memory for detection of an attack. The controller controls operations of the memory system through interfacing with a host. The first data reader is configured to read first data from the main memory based on address information from the controller. The second data reader is configured to store information relating to second data stored in the sub-memory and to read the second data from the sub-memory based on address information from the controller which is the same as the address information received by the first data reader. The comparator compares the first data read by the first data reader with the second data read by the second data reader to detect the attack. | 04-30-2009 |
20100115220 | COMPUTING SYSTEM INCLUDING MEMORY AND PROCESSOR - A computing system includes; a memory having first and second storage areas, and a processor sending a memory control signal to the memory to define a data access period during which data is accessed, and a read source control signal indicating whether the first storage area or the second storage area is to be accessed during the data access period. The memory activates a wait signal in response to the memory access signal and the read source control signal, and the processor is further configured to adjust the duration of the data access period in response to the wait signal. | 05-06-2010 |
20100229006 | Memory for Protecting Data, Memory System Including the Memory, and Method of Driving the Memory - A memory for protecting data includes a first storage area storing N-number of encryption keys, where N is a natural number, a second storage area receiving the N-number of encryption keys from the first storage area and storing again the received N-number of encryption keys, and a selection unit selecting one of the N-number of encryption keys stored in the second storage area according to a control signal, and encoding data input from outside the memory using a selected encryption key or decoding the data stored in the first storage area using the selected encryption key. | 09-09-2010 |
20100245048 | INTEGRATED CIRCUIT CARD SYSTEM AND A DATA TRANSMISSION METHOD THEREOF - An integrated circuit card system that includes a radio frequency (RF) integrated circuit configured to wirelessly communicate with an integrated circuit card reader; and an integrated circuit card, which is connected to the RF integrated circuit by a single wire, the integrated circuit card configured to change an amount of current of a data signal output from the integrated circuit card according to a transmission speed of a data signal input to the integrated circuit card from the RF integrated circuit. | 09-30-2010 |
20110101114 | Memory System and Data Reading Method Thereof - A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory. | 05-05-2011 |
20110225351 | MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME - A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms. | 09-15-2011 |
20120300548 | MEMORY SYSTEM AND DATA READING METHOD THEREOF - A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory. | 11-29-2012 |