Patent application number | Description | Published |
20080211089 | Interposer for die stacking in semiconductor packages and the method of making the same - Methods and apparatus for improved electrical, mechanical and thermal performance of stacked IC packages are described. An IC package comprises a substrate, a first die, a second die, and an interposer with an opening in a first surface of the interposer configured to accommodate the first die. The first IC die is attached a first surface of the substrate. The interposer is mounted on the first surface of the substrate such that the first IC die is placed within the opening in the interposer. The second die is mounted on a second surface of the interposer. Wire bonds couple bond pads on the first surfaces of IC die are coupled to the first surface of the substrate. A mold compound encapsulates the first IC die, the second IC die, the interposer and the wire bonds. | 09-04-2008 |
20080303124 | Lead frame-BGA package with enhanced thermal performance and I/O counts - Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads. | 12-11-2008 |
20090051010 | IC package sacrificial structures for crack propagation confinement - Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area. | 02-26-2009 |
20090102030 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 04-23-2009 |
20090108473 | DIE-ATTACH MATERIAL OVERFLOW CONTROL FOR DIE PROTECTION IN INTEGRATED CIRCUIT PACKAGES - Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in the first surface of the metal layer adjacent to the die-attach region. The adhesive material attaches a first surface of the die to the die-attach region and at least partially fills the recessed region(s). Excess adhesive material flows into the recessed region(s) during application of the die to the die-attach region, so that the side surfaces of the die remain substantially uncovered by the adhesive material. By preventing the excess adhesive material from covering the side surfaces of the die, the adhesive material is prevented from penetrating the side surfaces of the die, which could damage the die. | 04-30-2009 |
20100019360 | INTEGRATED CIRCUIT PACKAGE WITH ETCHED LEADFRAME FOR PACKAGE-ON-PACKAGE INTERCONNECTS - Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package. Signals of the first package may be electrically coupled with the second package at the exposed second ends of the interconnect members. Side surfaces of the interconnect members may be exposed at sides of the first package. | 01-28-2010 |
20120126396 | DIE DOWN DEVICE WITH THERMAL CONNECTOR - Methods and apparatuses for a die down device with a thermal connector are provided. In an embodiment, an integrated circuit (IC) device includes an IC die having opposing first and second surfaces, a thermal connector coupled to the first surface of the IC die, and a substrate. The second surface of the IC die is coupled to the substrate. The thermal connector is configured to be coupled to a circuit board. | 05-24-2012 |
20120187545 | DIRECT THROUGH VIA WAFER LEVEL FANOUT PACKAGE - Methods, systems, and apparatuses are described for improved integrated circuit packages. An integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing one or both surfaces of the semiconductor substrate. The die is mounted to the first surface of the semiconductor substrate. An encapsulating material encapsulates the die on the first surface of the semiconductor substrate. | 07-26-2012 |
20120223429 | Package 3D Interconnection and Method of Making Same - An integrated circuit (IC) package has a package member having a first surface and a second surface opposite the first surface. A first plurality of contact members is physically and electrically fixed to the second surface. An interposer substrate having a second plurality of contact members on one surface thereof which make physical and electrical contact with respective ones of the first plurality of contact members. The interposer substrate is configured to have at least one circuit member mounted to a second surface thereof opposite the one surface thereof. | 09-06-2012 |
20120225522 | Package 3D Interconnection and Method of Making Same - A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members. | 09-06-2012 |
20120234582 | MUTUAL CAPACITANCE AND MAGNETIC FIELD DISTRIBUTION CONTROL FOR TRANSMISSION LINES - Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material. | 09-20-2012 |
20130000968 | 1-Layer Interposer Substrate With Through-Substrate Posts - A method of manufacturing a printed circuit board is disclosed. A conductive metal layer is formed on a first surface of a dielectric substrate. One or more vias are formed through the substrate. A conductive metal layer is formed on the first surface of the substrate and is patterned to form conductive traces on the first surface of the substrate. A plating mask is formed on the second surface of the substrate. One or more openings are formed in the plating mask to correspond to the location of the via(s). Conductive metal is deposited in the via(s) sufficient to substantially fill the via(s) and make contact with the conductive metal layer on the first surface and substantially to the level of the plating mask. The plating mask is removed from the substrate such that one or more conductive posts extend outwardly from the second surface of the substrate. | 01-03-2013 |
20130075917 | Multi-Chip and Multi-Substrate Reconstitution Based Packaging - Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package. | 03-28-2013 |
20130078915 | Interposer Package Structure for Wireless Communication Element, Thermal Enhancement, and EMI Shielding - Embodiments of an interposer package structure are provided herein. Embodiments include a substrate having first and second opposing surfaces. An IC die electrically coupled to the first surface of the substrate. A plurality of contact members coupled to the first surface of the substrate. An interposer having a plurality of contact elements located on a first surface. Each conductive element coupled to a respective one of the plurality of contact members. The interposer is configured to facilitate wireless communication between the IC die and another device, heat spreading and electromagnetic interference shielding, | 03-28-2013 |
20130084816 | Wideband Power Efficient High Transmission Power Radio Frequency (RF) Transmitter - Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated. In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies. | 04-04-2013 |
20130154106 | Stacked Packaging Using Reconstituted Wafers - An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement. | 06-20-2013 |
20130168841 | Programmable Interposer with Conductive Particles - An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes. | 07-04-2013 |
20130168854 | Semiconductor Package with a Bridge Interposer - There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs). | 07-04-2013 |
20130168860 | Semiconductor Package with Ultra-Thin Interposer Without Through-Semiconductor Vias - There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer. | 07-04-2013 |
20130181354 | Semiconductor Interposer Having a Cavity for Intra-Interposer Die - A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate. | 07-18-2013 |
20130193587 | Semiconductor Package Having an Interposer Configured for Magnetic Signaling - There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance. | 08-01-2013 |
20130193996 | Semiconductor Package with Improved Testability - An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball. | 08-01-2013 |
20130214408 | Interposer Having Conductive Posts - There are disclosed herein various implementations of an interposer for use in semiconductor packaging. One exemplary implementation comprises a conductive post formed from a wire bond. A first end of the conductive post is mechanically joined to a conductive pad on a first surface of the interposer, while a second end of the conductive post is capable of making electrical connection to a contact body on an active surface of a semiconductor die. Such an interposer may include a rigid or flexible interposer dielectric. In one exemplary implementation, the interposer dielectric has a via formed therein, the conductive post being situated in the via and extending through a second surface of the interposer opposite the first surface. | 08-22-2013 |
20130214410 | ORGANIC INTERFACE SUBSTRATE HAVING INTERPOSER WITH THROUGH-SEMICONDUCTOR VIAS - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 08-22-2013 |
20130214426 | Semiconductor Package Including an Organic Substrate and Interposer Having Through-Semiconductor Vias - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 08-22-2013 |
20130221499 | Semiconductor Package with Integrated Electromagnetic Shielding - There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential. | 08-29-2013 |
20130221500 | System-In-Package with Integrated Socket - There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer. | 08-29-2013 |
20130221506 | Semiconductor Packages with Integrated Heat Spreaders - One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader. | 08-29-2013 |
20130221525 | Semiconductor Package with Integrated Selectively Conductive Film Interposer - There are disclosed herein various implementations of semiconductor packages having a selectively conductive film interposer. In one such implementation, a semiconductor package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, a selectively conductive film interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The selectively conductive film interposer may be configured to serve as an interposer and to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. | 08-29-2013 |
20140035162 | Interface Substrate with Interposer - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 02-06-2014 |
20140035163 | Semiconductor Package with Interface Substrate Having Interposer - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 02-06-2014 |
20140061886 | Semiconductor Package with Interposer - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 03-06-2014 |
20140061945 | Semiconductor Package Including a Substrate and an Interposer - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 03-06-2014 |
20140061946 | Semiconductor Package Including Interposer with Through-Semiconductor Vias - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 03-06-2014 |
20140103505 | DIE DOWN INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SPREADER AND LEADS - Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (QFN) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material. The peripherally positioned leads are attached to a first surface of the heat spreader, and the die is attached to the first surface of the heat spreader within a ring formed by the leads. The encapsulating material encapsulates the die on the heat spreader, encapsulates bond wires, and fills a space between the leads. A second surface of the heat spreader is exposed from the package. End portions of the leads have surfaces that are flush with a surface of the package opposite the second surface of the heat spreader, and that are used as lands for the package. | 04-17-2014 |
20140124940 | FLEXIBLE ROUTING FOR CHIP ON BOARD APPLICATIONS - Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion. | 05-08-2014 |
20140145300 | INTEGRATION OF CHIPS AND SILICON-BASED TRENCH CAPACITORS USING LOW PARASITIC SILICON-LEVEL CONNECTIONS - Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness. | 05-29-2014 |
20140151900 | STACKED PACKAGING USING RECONSTITUTED WAFERS - An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement. | 06-05-2014 |
20140235183 | INTERPOSER PACKAGE STRUCTURE FOR WIRELESS COMMUNICATION ELEMENT, THERMAL ENHANCEMENT, AND EMI SHIELDING - Embodiments of provide an integrated circuit (IC) device. The IC device can include a substrate having first and second opposing surfaces, an IC die electrically coupled to the first surface of the substrate, a plurality of contact members coupled to the first surface of the substrate, and an interposer. The interposer can include a plurality of contact elements located on a first surface thereof, each conductive element being coupled to a respective one of the plurality of contact members, and an antenna formed using a conductive layer of the interposer, the antenna being electrically coupled to the IC die through at least one of the plurality of contact elements and at least one of the plurality of contact members. | 08-21-2014 |