Khaderbad
Mrunai A. Khaderbad, Hsinchu City TW
Patent application number | Description | Published |
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20150262827 | SEMICONDUCTOR DEVICE WITH SIDEWALL PASSIVATION AND METHOD OF MAKING - One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening. | 09-17-2015 |
Mrunal A. Khaderbad, Hsinchu TW
Patent application number | Description | Published |
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20150187890 | METHOD OF FORMING TRENCH ON FINFET AND FINFET THEREOF - A method is provided for forming a trench on a FinFET. In an exemplary embodiment, a first inter-layer dielectric layer is formed between a first gate and a second gate of the FinFET in an interposed manner. A second inter-layer dielectric layer is formed above the first inter-layer dielectric layer, the first gate of the FinFET, and the second gate of the FinFET. A photoresist layer is formed above the second inter-layer dielectric layer. And part of the second inter-layer dielectric layer that is not below the photoresist layer is etched. | 07-02-2015 |
Mrunal A. Khaderbad, Hsin-Chu TW
Patent application number | Description | Published |
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20150279837 | Semiconductor Device Fabrication Method and Structure - A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer. | 10-01-2015 |