Patent application number | Description | Published |
20120319713 | AUTOMATIC PROBE CONFIGURATION STATION AND METHOD THEREFOR - A probe system for facilitating the inspection of a device under test. System incorporates a storage rack; a probe bar gantry assembly; a probe assembly configured to electrically mate the device under test; and a robot system for picking the probe assembly from the storage rack and deliver the probe assembly to the probe bar gantry. The robot system is also enabled to pick a probe assembly from the probe bar gantry and deliver the probe assembly to the storage rack. The probe assembly includes a clamping assembly for attaching the probe assembly to the probe bar gantry or the storage rack. The probe assembly may include an array of contact pins configured to mate with conductive pads on the device under test when the probe assembly is installed on the probe bar gantry assembly. | 12-20-2012 |
20150236566 | Integrated Two-Axis Lift-Rotation Motor Center Pedestal In Multi-Wafer Carousel ALD - Apparatus and methods for processing a semiconductor wafer including a two-axis lift-rotation motor center pedestal with vacuum capabilities. Wafers are subjected to a pressure differential between the top surface and bottom surface so that sufficient force prevents the wafer from moving during processing, the pressure differential generated by applying a decreased pressure to the back side of the wafer through interface with the motor assembly. | 08-20-2015 |
20150345022 | Apparatus And Methods For Injector To Substrate Gap Control - Described are apparatus and methods for processing a semiconductor wafer in which the gap between the wafer surface and the gas distribution assembly remains uniform and of known thickness. The wafer is positioned within a susceptor assembly and the assembly is lifted toward the gas distribution assembly using actuators. The wafer can be lifted toward the gas distribution assembly by creating a fluid bearing below and/or above the wafer. | 12-03-2015 |
20150376786 | Apparatus And Methods For Carousel Atomic Layer Deposition - Gas distribution assemblies and susceptor assemblies made up of a plurality of pie-shaped segments which can be individually leveled, moved or changed. Processing chambers comprising the gas distribution assemblies, the susceptor assemblies and sensors with feedback circuits to adjust the gap between the susceptor and gas distribution assembly are also described. Methods of using the gas distribution assemblies, susceptor assemblies and processing chambers are also described. | 12-31-2015 |
20150376790 | Apparatus And Methods For Differential Pressure Chucking Of Substrates - Apparatus and methods for processing a semiconductor wafer so that the wafer remains in place during processing. The wafer is subjected to a pressure differential between the top surface and bottom surface so that sufficient force prevents the wafer from moving during processing. | 12-31-2015 |
20160027675 | Position And Temperature Monitoring Of ALD Platen Susceptor - Apparatus and methods of measuring and controlling the gap between a susceptor assembly and a gas distribution assembly are described. Apparatus and methods for positional control and temperature control for wafer transfer purposes are also described. | 01-28-2016 |
Patent application number | Description | Published |
20140115224 | MEMORY INTERCONNECT NETWORK ARCHITECTURE FOR VECTOR PROCESSOR - The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network. | 04-24-2014 |
20140115301 | PROCESSOR ARCHITECTURE AND METHOD FOR SIMPLIFYING PROGRAMMING SINGLE INSTRUCTION, MULTIPLE DATA WITHIN A REGISTER - The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element. | 04-24-2014 |
20140281435 | METHOD TO PARALLEIZE LOOPS IN THE PRESENCE OF POSSIBLE MEMORY ALIASES - In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated. | 09-18-2014 |