Patent application number | Description | Published |
20080301475 | PERFORMANCE CONSERVING METHOD FOR REDUCING POWER CONSUMPTION IN A SERVER SYSTEM - A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity. | 12-04-2008 |
20080307238 | System for Unified Management of Power, Performance, and Thermals in Computer Systems - A system is provided for unified management of power, performance, and thermals in computer systems. This system incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The system employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The system provides interfaces for user-level interaction. The system also employs methods to address power/thermal concerns at multiple timescales. In addition, the system improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion. | 12-11-2008 |
20100011227 | SYSTEM AND METHOD FOR MEASUREMENT-BASED POWER AND ENERGY ACCOUNTING FOR VIRTUAL MACHINES - A method for measurement-based power and energy accounting for virtual machines distributed among at least one hosting device is disclosed. The method comprising determining an energy for the hosting device during a first time interval and a second time interval, partitioning a difference in the determined energy among virtual machines within a plurality of regions of the hosting device, determining a level of activity of each of the resources in each virtual machine within a corresponding one of the regions, determining an energy of each resource in each corresponding virtual machine wherein energy associated with resources shared among an plurality of virtual machines are allocated to a corresponding one of the virtual machines based on a number of requests made to the shared resource by the corresponding virtual machine, determining a total energy for each of the virtual machines in corresponding regions based on a level of activity of the virtual machine and the energy associated with the corresponding shared resources, and determining a power for each of the virtual machines by dividing the determined total energy by a length of the time interval. | 01-14-2010 |
20100115343 | METHOD FOR AUTOMATED PROCESSOR POWER MANAGEMENT FOR BETTER ENERGY-EFFICIENCY - Semiconductor device circuits and methods are provided for adjusting core processor performance and energy-efficiency based on usage metrics. Metric detection, performance state selection, and adjustment are done in digital logic hardware without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Mapping usage and state information to desired processor power-performance states is also provided in circuitry rather than firmware or power control software. The mapping values may be programmable software or firmware, but detection, selection, and adjustment occur automatically in hardware without intervening input from firmware or software. | 05-06-2010 |
20100146316 | Optimizing Power Consumption by Tracking How Program Runtime Performance Metrics Respond to Changes in Operating Frequency - A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted. | 06-10-2010 |
20100218029 | System and Method for Managing the Power-Performance Range of an Application - Semiconductor device circuits and methods are provided for adjusting core processor performance based on usage metrics. Metric detection and adjustment are performed in digital logic hardware guided by registers providing maximum and minimum frequency settings, without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Power-performance drivers provide applications or the operating system ability to specify maximum and minimum frequency requirements. | 08-26-2010 |
20100268968 | MANAGING PROCESSOR POWER-PERFORMANCE STATES - Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate. The voltage value, frequency value, and unique pointer of a given pstate definition are configurable, during operation of the data processing system, by the power manager module in response to changes in the operating parameters of the data processing system. | 10-21-2010 |
20100268974 | Using Power Proxies Combined with On-Chip Actuators to Meet a Defined Power Target - A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value. | 10-21-2010 |
20100332872 | Priority-Based Power Capping in Data Processing Systems - A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system. | 12-30-2010 |
20110083021 | RELIABLE SETTING OF VOLTAGE AND FREQUENCY IN A MICROPROCESSOR - Managing operations associated with one or more voltage changes and one or more frequency changes. A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operations are transmitted by the processors to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by the system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed one or more future voltage changes are suspended. | 04-07-2011 |
20110113270 | Dynamic Voltage and Frequency Scaling (DVFS) Control for Simultaneous Multi-Threading (SMT) Processors - A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors. | 05-12-2011 |
20110145555 | Controlling Power Management Policies on a Per Partition Basis in a Virtualized Environment - A mechanism is provided for controlling power management policies on a per logical partition basis. A power management mechanism in a data processing system receives a notification that the logical partition has been generated, a set of processing units associated with the logical partition, and a current power management policy to be implemented for the logical partition. The power management mechanism adds the logical partition and the set of processing units to a list of logical partitions. The power management mechanism initializes the set of processing units based on settings for the set of processing units in the current power management policy. The power management mechanism notifies a virtualization mechanism that the set of processing units are running at a specified performance level in order for the logical partition to start executing tasks on the set of processing units. | 06-16-2011 |
20110154322 | Preserving a Dedicated Temporary Allocation Virtualization Function in a Power Management Environment - A mechanism is provided for temporarily allocating dedicated processors to a shared processor pool. A virtual machine monitor determines whether a temporary allocation associated with an identified dedicated processor is long-term or short-term. Responsive to the temporary allocation being long-term, the virtual machine monitor determines whether an operating frequency of the identified dedicated processor is within a predetermined threshold of an operating frequency of one or more operating systems utilizing the shared processor pool. Responsive to the operating frequency of the identified dedicated processor failing to be within the predetermined threshold, the virtual machine monitor either increases or decreases the frequency of the identified dedicated processor to be within the predetermined threshold of the operating frequency of the one or more operating systems utilizing the shared processor pool and temporarily allocates the identified dedicated processor to the shared processor pool. | 06-23-2011 |
20110154323 | Controlling Depth and Latency of Exit of a Virtual Processor's Idle State in a Power Management Environment - A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor. | 06-23-2011 |
20110173468 | Oversubscribing Branch Circuits While Lowering Power Distribution Costs - A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element. | 07-14-2011 |
20110178652 | Dynamically Adjusting an Operating State of a Data Processing System Running Under a Power Cap - A mechanism is provided for dynamically power capping one or more units. A power capping mechanism sets a counter value corresponding to an initial energy budget assigned to a unit for a given interval. Responsive to the unit receiving an operation to perform during the given interval, the power capping mechanism decrements the counter value by a decrement value. Responsive to the given interval expiring, the power capping mechanism sends the counter value to a power control loop in the data processing system, receives a new energy budget from the power control loop, and resets the counter value to a value corresponding to the new energy budget assigned to the unit for a next interval. | 07-21-2011 |
20110292594 | Scalable Space-Optimized and Energy-Efficient Computing System - A scalable space-optimized and energy-efficient computing system is provided. The computing system comprises a plurality of modular compartments in at least one level of a frame configured in a hexadron configuration. The computing system also comprises an air inlet, an air mixing plenum, and at least one fan. In the computing system the plurality of modular compartments are affixed above the air inlet, the air mixing plenum is affixed above the plurality of modular compartments, and the at least one fan is affixed above the air mixing plenum. When at least one module is inserted into one of the plurality of modular compartments, the module couples to a backplane within the frame. | 12-01-2011 |
20110292597 | Stackable Module for Energy-Efficient Computing Systems - A modular processing module is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors coupled to the circuit board, and a plurality of processing nodes coupled to the circuit board. Each processing module side in the set of processing module sides couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system. | 12-01-2011 |
20110296097 | Mechanisms for Reducing DRAM Power Consumption - Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells. | 12-01-2011 |
20110296118 | Dynamic Row-Width Memory - A mechanism is provided for dynamic row-width memory. The memory adapts row width to usage based on memory controller and memory management system software control. The mechanism uses an organization and control of memory array access logic. The memory controller may receive an explicit command using existing column address lines or using a command line into the memory controller. In a first option, the memory controller receives a row width and disables the unused columns and turns off the unused sense amps. In a second option, the memory controller receives a row width and adjusts row count, keeping the number of active cells constant. In a third option, the memory controller receives a row width and adjusts a number of banks. | 12-01-2011 |
20110296138 | FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS - A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute. | 12-01-2011 |
20110296149 | Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs - Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction. | 12-01-2011 |
20110320840 | Transparently Increasing Power Savings in a Power Management Environment - A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode. | 12-29-2011 |
20120066519 | DATA CENTER POWER CONVERSION EFFICIENCY MANAGEMENT - A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply. | 03-15-2012 |
20120079500 | PROCESSOR USAGE ACCOUNTING USING WORK-RATE MEASUREMENTS - Accounting charges are assigned to workloads by measuring a relative use of computing resources by the workloads, then scaling the results using determined work-rate for the corresponding workload. Usage metrics for the individual resources may be selectable for the resources being measured and the work-rates may be determined from an analytical model or from empirical model that determines work-rates from an indication of processor throughput. Under single workload conditions on a platform, or other suitable conditions, a workload type may be used to select the particular usage metrics applied for the various resources. | 03-29-2012 |
20120096293 | Directed Resource Folding for Power Management - A mechanism is provided for directed resource folding for power management. The mechanism receives a set of static platform characteristics and a set of dynamic platform characteristics for a set of resources associated with the data processing system thereby forming characteristic information. The mechanism determines whether one or more conditions have been met for each resource in the set of resources using the characteristic information. Responsive to the one or more conditions being met, the mechanism performs a resource optimization to determine at least one of a first subset of resources in the set of resources to keep active and a second subset of resources in the set of resources to dynamically fold. Based on the resource optimization, the mechanism performs either a virtual resource optimization to optimally schedule the first subset of resources or a physical resource optimization to dynamically fold the second subset of resources. | 04-19-2012 |
20120116599 | Allocation of Energy Budgets to Individual Partitions - A mechanism is provided for allocating energy budgets to a plurality of logical partitions. An overall energy budget for the data processing system and a total of a set of requested initial energy budgets for the plurality of partitions are determined. A determination is made as to whether the total of the set of requested initial energy budgets for the plurality of partitions is greater than the overall energy budget for the data processing system. Responsive to the total of the set of requested initial energy budgets exceeding the overall energy budget, an initial energy budget is allocated to each partition in the plurality of partitions based on at least one of priority or proportionality of each partition in the plurality of partitions such that a total of the initial energy budgets for the plurality of partitions does not exceed the overall energy budget of the data processing system. | 05-10-2012 |
20120191946 | FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS - A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute. | 07-26-2012 |
20120198452 | CONTROLLING DEPTH AND LATENCY OF EXIT OF A VIRTUAL PROCESSOR'S IDLE STATE IN A POWER MANAGEMENT ENVIRONMENT - A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor. | 08-02-2012 |
20120233479 | Oversubscribing Branch Circuits While Lowering Power Distribution Costs - A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element. | 09-13-2012 |
20120240109 | HARDWARE CHARACTERIZATION IN VIRTUAL ENVIRONMENTS - A, system, and computer program product for hardware characterization in a virtual environment are provided in the illustrative embodiments. The hardware resource is allocated to a test virtual machine (VM). A characterization workload is configured to execute in the test VM to characterize a parameter of the hardware resource. The characterization workload is caused to execute on the test VM. A first result of the characterization workload execution is received from the test VM, wherein the result assigns a value to a characteristic of the hardware resource indicative of a behavior of the hardware resource under a set of circumstances. | 09-20-2012 |
20120240115 | HARDWARE CHARACTERIZATION IN VIRTUAL ENVIRONMENTS - A method for hardware characterization in a virtual environment is provided in the illustrative embodiments. The hardware resource is allocated to a test virtual machine (VM). A characterization workload is configured to execute in the test VM to characterize a parameter of the hardware resource. The characterization workload is caused to execute on the test VM. A first result of the characterization workload execution is received from the test VM, wherein the result assigns a value to a characteristic of the hardware resource indicative of a behavior of the hardware resource under a set of circumstances. | 09-20-2012 |
20120324263 | Priority-Based Power Capping in Data Processing Systems - A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system. | 12-20-2012 |
20120324264 | Priority-Based Power Capping in Data Processing Systems - A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system. | 12-20-2012 |
20120330802 | METHOD AND APPARATUS FOR SUPPORTING MEMORY USAGE ACCOUNTING - An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. | 12-27-2012 |
20120330803 | METHOD AND APPARATUS FOR SUPPORTING MEMORY USAGE THROTTLING - An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value. | 12-27-2012 |
20120331231 | METHOD AND APPARATUS FOR SUPPORTING MEMORY USAGE THROTTLING - An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value. | 12-27-2012 |
20130033306 | PERFORMANCE OF DIGITAL CIRCUITS USING CURRENT MANAGEMENT - A method, system, and computer program product for improving the performance of a digital circuit are provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value. | 02-07-2013 |
20130035797 | PERFORMANCE OF DIGITAL CIRCUITS USING CURRENT MANAGEMENT - A method for improving the performance of a digital circuit is provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value. | 02-07-2013 |
20130076343 | NON-CONTACT CURRENT AND VOLTAGE SENSING CLAMP - A clamping current and voltage sensor provides an isolated and convenient technique for measuring current passing through a conductor such as an AC branch circuit wire, as well as providing an indication of an electrostatic potential on the wire, which can be used to indicate the phase of the voltage on the wire, and optionally a magnitude of the voltage. The device includes a body formed from two handle portions that contain the current and voltage sensors within an aperture at the distal end, which may be a ferrite cylinder with a hall effect sensor disposed in a gap along the circumference to measure current, or alternatively a winding provided through the cylinder along its axis and a capacitive plate or wire disposed adjacent to, or within, the ferrite cylinder to provide the indication of the voltage. When the handles are compressed the aperture is opened to permit insertion of a wire for measurement. | 03-28-2013 |
20130124810 | INCREASING MEMORY CAPACITY IN POWER-CONSTRAINED SYSTEMS - A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay. | 05-16-2013 |
20130124814 | INCREASING MEMORY CAPACITY IN POWER-CONSTRAINED SYSTEMS - A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay. | 05-16-2013 |
20130151577 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 06-13-2013 |
20130151578 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 06-13-2013 |
20130151867 | SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT - A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic. | 06-13-2013 |
20130304997 | Command Throttling for Multi-Channel Duty-Cycle Based Memory Power Management - A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic. | 11-14-2013 |
20130325378 | Predicting Energy Savings - A mechanism is provided for estimating energy/power consumption of a fixed-frequency operating mode while system is running in dynamic power management mode. For each time interval in a plurality of time intervals within a time period: a first processor identifies a modeled total nominal power value for at least one second processor during a current time interval, stores the modeled total nominal power value for the current time interval in a storage, identifies a dynamic power management mode power value for the at least one second processor in the data processing system during the current interval, and stores the dynamic power management mode power value for the current time interval in the storage. Responsive to the time period expiring, a comparison is produced of a plurality of modeled total nominal power values and a plurality of dynamic power management mode power values over the time period. | 12-05-2013 |
20140013126 | BRANCH CIRCUIT DETERMINATION WITHOUT EXTERNAL SYNCHRONIZATION - A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit. | 01-09-2014 |
20140062459 | FLEXIBLE CURRENT AND VOLTAGE SENSOR - A flexible current and voltage sensor provides ease of installation of a current sensor, and optionally a voltage sensor in application such as AC branch circuit wire measurements, which may require installation in dense wiring conditions and/or in live panels where insulating gloves must be worn. The sensor includes at least one flexible ferromagnetic strip that is affixed to a current sensing device at a first end. The second end is secured to the other side of the current sensing device or to another flexible ferromagnetic strip extending from the other side of the current sensing device to form a loop providing a closed pathway for magnetic flux. A voltage sensor may be provided by metal foil affixed to the inside of the flexible ferromagnetic strip. A clamp body, which can be a spring loaded handle operated clamp or a locking fastener, can secure the ferromagnetic strip around the wire. | 03-06-2014 |
20140100804 | Statistical Determination of Power-Circuit Connectivity - A mechanism is provided for statistical determination of power circuit connectivity based on signal detection in a circuit. Signal data from the circuit gathered and a determination is made as to whether a signal of interest is present in the gathered signal data from the circuit using a statistical analysis of the gathered signal data. The statistical analysis comprises using a mean current value and statistical deviation of the current value of the signal data over a predetermined period of time to compute a confidence range. The confidence range is compared to a first threshold and a second threshold. A determination is made that the signal is present in response to the confidence range being above the first threshold. A determination is made that the signal is not present in response to the confidence range being below the second threshold. | 04-10-2014 |
20140136786 | ASYNCHRONOUS PERSISTENT STORES FOR TRANSACTIONS - A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction. | 05-15-2014 |
20140149750 | COMPUTING SYSTEM VOLTAGE CONTROL - An apparatus including a voltage safety verification unit (VSVU) configured to receive an indication of a first performance state, the first performance state being associated with a first voltage. The first performance state applies to at least one computing system component and the indication is received by a computing system component distinct from the requesting computing system component. The VSVU is configured to receive an indication of a second performance state. The second performance state is associated with a second voltage that is not equal to the first voltage. The VSVU is configured to determine whether the second performance state is within a range defined by a minimum and maximum performance state. Responsive to a determination that the second performance state is within the, the VSVU is configured to set the voltage of the at least one computing system component equal to the voltage associated with the second performance state. | 05-29-2014 |
20140149751 | SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT - A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector. | 05-29-2014 |
20140149752 | ASSOCIATING ENERGY CONSUMPTION WITH A VIRTUAL MACHINE - Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory. | 05-29-2014 |
20140149755 | DECOUPLED POWER AND PERFORMANCE ALLOCATION IN A MULTIPROCESSING SYSTEM - A performance supervisor computer program product is configured to set a maximum and a minimum performance operating limit for a plurality of processing units in accordance with a set of one or more rules enforced by the performance supervisor. Each of the plurality of processing units has logic configured to ensure a request for an operational setting complies with the maximum and minimum operating limits. Each of the plurality of processing units is configured to output a request for a limit compliant operational setting to a performance controller. The performance controller is configured to actuate the operational request. | 05-29-2014 |
20140149760 | DISTRIBUTED POWER BUDGETING - A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component. | 05-29-2014 |
20140149761 | DISTRIBUTED POWER BUDGETING - Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component. | 05-29-2014 |
20140149762 | DECOUPLED POWER AND PERFORMANCE ALLOCATION IN A MULTIPROCESSING SYSTEM - Embodiments of the inventive subject matter include setting minimum and maximum performance operating limits for each of a plurality of controllers. The operating limits are set in accordance with performance rules imposed on the system. In response to a request to change operation of a processing unit to a requested operational setting, it is determined whether the requested operational setting complies with the minimum and maximum performance operating limits. The minimum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the minimum performance operating limit. The maximum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the maximum performance operating limit. The requested operational setting is sent to a performance controller if the requested operational setting complies with the minimum and maximum performance operating limits. | 05-29-2014 |
20140149763 | COMPUTING SYSTEM VOLTAGE CONTROL - Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state. | 05-29-2014 |
20140149779 | ASSOCIATING ENERGY CONSUMPTION WITH A VIRTUAL MACHINE - Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory. | 05-29-2014 |
20140156100 | DATA CENTER POWER CONVERSION EFFICIENCY MANAGEMENT - A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply. | 06-05-2014 |
20140157013 | DATA CENTER POWER CONVERSION EFFICIENCY MANAGEMENT - A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply. | 06-05-2014 |
20140210453 | MULTI-BRANCH CURRENT/VOLTAGE SENSOR ARRAY - A sensor array including multiple current sensors provides input for power measurement and management systems. The sensor array includes split ferrite cylinder portions connected by a frame, so that when the array is installed around multiple branch circuits in a power distribution panel or raceway, the ferrite cylinders are completed to surround the conductor(s) of the associated branch circuit. Voltage sensing may also be incorporated within the sensors by providing an electrically conductive plate, wire or other element that capacitively couples to the corresponding wire(s). | 07-31-2014 |
20140244212 | Monitoring Aging of Silicon in an Integrated Circuit Device - A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement. | 08-28-2014 |
20150074162 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 03-12-2015 |
20150081039 | Dynamic Adjustment of Operational Parameters to Compensate for Sensor Based Measurements of Circuit Degradation - A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified. | 03-19-2015 |
20150081044 | Dynamic Adjustment of Operational Parameters to Compensate for Sensor Based Measurements of Circuit Degradation - A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified. | 03-19-2015 |
20150089263 | SYSTEM-WIDE POWER CONSERVATION USING MEMORY CACHE - A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down. | 03-26-2015 |