Kang Joon
Kang Joon Lee, Seoul KR
Patent application number | Description | Published |
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20110259914 | DUAL-STRUCTURE TUBE VESSEL AND METHOD OF PRODUCING THE SAME - A dual-structure tube vessel and a method of producing the tube vessel are disclosed. The dual-structure tube vessel includes a cylindrical vessel body and a neck integrated with the vessel body into a single structure, and further includes: a body partitioning sheet provided in the vessel body and partitioning the interior of the vessel body into two sections; and a neck partitioning sheet provided in the neck and partitioning the interior of the neck into two sections. The vessel body and the body partitioning sheet may be fabricated using three sheets of material or one sheet of material. Further, the body partitioning sheet has a width equal to an inner circumference of a larger one of the two sections of the vessel body. Further, each of the vessel body and the body partitioning sheet is made of a threefold laminated sheet with a polyethylene/aluminum/polyethylene layered structure. | 10-27-2011 |
Kang Joon Lee, Yongin-Si KR
Patent application number | Description | Published |
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20120299197 | SEMICONDUCTOR PACKAGES - Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter. | 11-29-2012 |
Kang Joon Lee, Hwaseong-Si KR
Patent application number | Description | Published |
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20160141271 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate. The upper package includes an upper package substrate and an upper semiconductor chip thereon. The lower mold layer includes a guide portion extending along a vertical direction from an edge of the lower package substrate toward the upper package. | 05-19-2016 |