Patent application number | Description | Published |
20080311727 | METHOD OF CUTTING A WAFER - In a method of cutting a wafer, a supporting member is attached to an upper surface of the wafer on which semiconductor chips are formed. An opening is formed at a lower surface of the wafer along a scribe lane of the wafer. The lower surface of the wafer may be plasma-etched to reduce a thickness of the wafer. A tensile tape may be attached to the lower surface of the wafer. Here, the tensile tape includes sequentially stacked tensile films having different tensile modules. The supporting member is then removed. The tensile tape is cooled to increase the tensile modules between the tensile films. The tensile tape is tensed until the tensile films are cut using the tensile modules difference to separate the tensile tape from the semiconductor chips. Thus, the lower surface of the wafer may be plasma-etched without using an etching mask. | 12-18-2008 |
20080315408 | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same - Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups. | 12-25-2008 |
20090278249 | Printed circuit board and method thereof and a solder ball land and method thereof - A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance. | 11-12-2009 |
20110110062 | Stack-type semiconductor device having chips having different backside structure and electronic apparatus including the same - A stack-type semiconductor device including semiconductor chips having different backside structures and an electronic apparatus including the stack-type semiconductor device include: a base frame for a semiconductor device; a first semiconductor chip that is mounted on the base frame and has a bottom surface having a first surface roughness; and a second semiconductor chip that is mounted on the first semiconductor chip and has a bottom surface having a second surface roughness, wherein the second surface roughness is greater than the first surface roughness by 1.2 nm or more. The stack-type semiconductor device is manufactured to be thin while cracking of the first semiconductor chip is prevented. In addition, changes in data caused by charge loss resulting from diffusion of metal ions, which can occur when a stack-type semiconductor device is a memory device, is prevented. | 05-12-2011 |
20110318887 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 12-29-2011 |
20130203220 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 08-08-2013 |
20130223001 | PRINTED CIRCUIT BOARD AND MEMORY MODULE COMPRISING THE SAME - A printed circuit board (PCB) comprises an internal wiring layer, an insulating layer on the internal wiring layer, a via hole extending through the insulating layer, and an external wiring layer on the insulating layer. The internal wiring layer comprises at least one metal wiring layer. The via hole exposes the internal wiring layer. The external wiring layer is electrically connected to the internal wiring layer. The external wiring layer includes a mounting area on which a semiconductor chip is disposed and a non-mounting area on which a semiconductor chip is not disposed. A thickness of the mounting area is less than a thickness of the non-mounting area. | 08-29-2013 |
20130337616 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND UNDERFILL EQUIPMENT FOR THE SAME - A method of fabricating a semiconductor device comprises loading a circuit board including a semiconductor chip into underfill equipment, positioning the circuit board on a depositing chuck of the underfill equipment, filling an underfill material in a space between the semiconductor chip and the circuit board placed on the depositing chuck; transferring the circuit board including the underfill material so that it is positioned on a post-treatment chuck of the underfill equipment; heating the underfill material of the circuit board placed on the post-treatment chuck in a vacuum state, and unloading the circuit board, of which the underfill material has been heated in the vacuum state, from the underfill equipment. | 12-19-2013 |
20140062496 | TEST APPARATUS FOR SEMICONDUCTOR PACKAGE - A test apparatus for a semiconductor package comprising an X-ray analyzer acquiring an X-ray image of the semiconductor package and detecting a thickness of the semiconductor package from the X-ray image, and a thermal reaction analyzer applying a voltage to the semiconductor package and detecting a failure position of the semiconductor package using a surface temperature of the semiconductor package and the thickness of the semiconductor package may be provided. | 03-06-2014 |
20140242752 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. | 08-28-2014 |