Patent application number | Description | Published |
20090170302 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR - A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer. | 07-02-2009 |
20100096691 | SEMICONDUCTOR DEVICE HAVING VERTICALLY ALIGNED PILLAR STRUCTURES THAT HAVE FLAT SIDE SURFACES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having vertically aligned transistors made from pillar structures that have flat side surfaces is presented. The semiconductor device includes a semiconductor substrate, spacers, and gates. The semiconductor substrate has lo pillar structures that have flat side surfaces. The spacers are on sidewalls only on the upper portions of the pillar structures. The gates surround lower portions of the pillar structures. | 04-22-2010 |
20100184359 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic. | 07-22-2010 |
20110003459 | METHOD FOR FABRICATING BURIED GATE USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 01-06-2011 |
20110156262 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs. | 06-30-2011 |
20120280313 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs. | 11-08-2012 |
20130137258 | METHOD FOR FABRICATING BURIED GATES USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 05-30-2013 |