Patent application number | Description | Published |
20080201597 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 08-21-2008 |
20080291758 | READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA - Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting. | 11-27-2008 |
20090296503 | READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA - Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting. | 12-03-2009 |
20110074477 | Techniques for Providing Reduced Duty Cycle Distortion - A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting. | 03-31-2011 |
20110175657 | DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS - Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle. | 07-21-2011 |
20110221497 | METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS - Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements. | 09-15-2011 |
20120106264 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 05-03-2012 |
20130278290 | PROGRAMMABLE HIGH-SPEED I/O INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 10-24-2013 |
20140340125 | PROGRAMMABLE HIGH-SPEED I/O INTERFACE - Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application. | 11-20-2014 |
Patent application number | Description | Published |
20100290180 | USB FLASH DISK WITH NONE-JOINT METALLIC HOUSING - A USB flash disk with a none-joint metallic housing, the main point is that the USB flash disk is formed by inserting an internal structure composed of a printed circuit board, a metallic tray and an insulation upper seat in the metallic housing which is a none-joint rectangular pipe formed by drawing shaping. | 11-18-2010 |
20100290181 | USB FLASH DISK - A USB flash disk is disclosed as being inserted therein with an internal structure composed of a printed circuit board, a metallic tray, a lower insulation seat and a clamping strip unit etc. for completing the USB flash disk. | 11-18-2010 |
20100321878 | RETRACTABLE USB MEMORY STICK - A retractable USB memory stick includes a metal casing formed of a seamless flat tube having opposing front opening and rear opening, a sliding slot located on one peripheral wall thereof, and first and second locating holes located on the sliding slot, a PC board having a front USB interface circuit and a rear memory IC package, and an insulation PC board holder holding the PC board and slidably mounted in the metal casing. The insulation PC board holder has a spring strip bridged on the outside wall thereof, a sliding block located on the spring strip and forced by the spring power of the spring strip into the sliding slot of the metal casing, and a retaining block protruded from the sliding block for selectively engaging the first locating hole or second locating hole of the metal casing to lock the insulation PC board holder to the metal casing in the extended position and received position. | 12-23-2010 |
20110011146 | METHOD OF FORMING A TENON ON ONE SIDE OF A METAL PLATE MEMBER - A method of forming a tenon on one side of a metal plate member by means of punching the wall of one side of the metal plate member with a punch or punches to form a protrusion and then punching the protrusion with a punch rod to extend the height of the protrusion and to deform the protrusion into a tubular configuration. | 01-20-2011 |
20110013354 | MEMORY STICK - A memory stick includes a | 01-20-2011 |
20120327610 | USB MEMORY STICK - A USB memory stick includes a metal shell structure defining opposing top opening and bottom opening and a locating hole, a PC board formed of a USB interface circuit and a memory chip package, and a tray, which includes a support panel supporting the PC board, a clip extended from one side of the support panel and clamped on the memory chip package of the PC board, a spring plate extended from the clip and pressed on the PC board against the support panel, and an oblique retaining leaf obliquely extended from the spring plate and engaged into the locating hole of the metal shell structure. | 12-27-2012 |
20130021741 | BOOKMARK MEMORY STICK - A bookmark memory stick includes a PC board, a flat, elongated insulative holder shell having a recessed accommodation portion accommodating the PC board and a retaining hole disposed near the top end thereof, a metal cover shell surrounding the insulative holder shell and a clip, which has a transverse locating base fitted into a locating notch at the top end of the insulative holder shell, a double-bevelled clamping plate obliquely downwardly extended from the front side of the transverse locating base toward the inside of the metal cover shell and stopped against a inverted T-plate of the insulative holder shell and then curved obliquely outwardly for clamping a sheet member on the inverted T-plate, a back plate extended from the back side of the transverse locating base and inserted into the inner top side of the metal cover shell, and a hook plate obliquely extended from the back plate and engaged into the retaining hole of the insulative holder shell. | 01-24-2013 |
20130044423 | MEMORY STICK HAVING A LOCK DEVICE - A memory stick having a lock device includes a metal housing, a PC board, a tray carrying the PC board, lock body, a lock body having a positioning block press-fitted into a top opening of the metal housing and a locating block engaged into a top notch of the metal housing and adapted for accommodating an upper part of the tray and a part of an IC package circuit of the PC board for enabling the USB interface circuit to be suspending in a bottom opening of the metal housing, and a locking mechanism for enabling the memory stick to be locked to an external object. | 02-21-2013 |
20130114201 | SIDE-PUSH TYPE RETRACTABLE USB MEMORY STICK - A side-push retractable USB memory stick includes a PC board providing a data storage function, an insulative PC board holder accommodating the PC board and having a springy plate located on one lateral side thereof and a press portion outwardly protruded from the springy plate, a housing surrounding the insulative PC board holder and having a sliding slot located on one lateral side thereof for receiving the press portion and enabling the press portion to be operated by an external force to move a metal shield and a USB interface circuit of the PC board in and out of a front opening of the housing. A rear end block closed on a rear open side of the housing, and a front end block press-fitted into the front opening and defining a through hole for passing the metal shield and the USB interface circuit in and out of the housing. | 05-09-2013 |
20130265709 | USB MEMORY STICK WITH A HINGED SAFETY HOOK - A USB memory stick includes comprises a casing comprising opposing top and bottom sides and a bottom opening in said bottom side, a PC board comprising a USB interface circuit and a memory chip package, a tray holding the PC board in the casing, a safety hook for fastening to a belt or strip-like object, and a hinge coupled between the casing and the safety hook for allowing a limited angle of rotation between the casing and the safety hook. | 10-10-2013 |
Patent application number | Description | Published |
20100045349 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 02-25-2010 |
20110227606 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 09-22-2011 |
20120146700 | MULTIPLE DATA RATE INTERFACE ARCHITECTURE - Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation. | 06-14-2012 |
20140049287 | MULTIPLE DATA RATE INTERFACE ARCHITECTURE - Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation. | 02-20-2014 |
Patent application number | Description | Published |
20090213038 | Head Mounted Display and Real-Time Video Device - A head mounted display is disclosed in this invention. The head mounted display includes a display module, a removable supporting frame, and a removable clamping device. The display module is connected to a multi-media player. The removable supporting frame is disposed on the display module. The removable clamping device is disposed on the display module so as to clip eyeglasses of a user. A real-time video device is also disclosed in this invention. The real-time video device includes an image capturing device, a receiving device, and a head mounted display. The image capturing device is able to capture a motion image of a user continuously and transfer a signal of the motion image. The receiving device is used to receive the signal of the motion image. The head mounted display is mounted on the head of the user; the motion image is displayed on a display element of the head mounted display instantaneously. | 08-27-2009 |
20140211407 | USB MEMORY STICK - A USB memory stick includes housing having a frame hole, a tray providing a fastening structure, and a memory attached to the tray and mounted with the tray in the housing. The memory includes a mating fastening structure fastened to the fastening structure of the tray, a stepped bottom wall formed of a plurality of steps rising one behind another, a plurality of vertical clearance compensation spring leaves respectively disposed corresponding to the steps, and a mating locating block forced into engagement with the frame hole of the housing. | 07-31-2014 |
20150195933 | MEMORY STICK - A memory stick includes a casing having a connection member at a top end thereof for connection to a personal item and an opening at a bottom end thereof, a positioning tray insertable through the opening of the casing for positioning in the casing and having an angled upper bending plate extended from a top end thereof and defining with a bottom wall thereof a clamping space and an elastically deformable recessed portion defined in the angled upper bending plate, and a flash memory detachably inserted into the clamping space of the positioning tray and held down in place by the recessed portion. | 07-09-2015 |