Patent application number | Description | Published |
20090302468 | Printed circuit board comprising semiconductor chip and method of manufacturing the same - Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip. | 12-10-2009 |
20100193932 | WAFER LEVEL PACKAGE FOR HEAT DISSIPATION AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate. | 08-05-2010 |
20100320624 | DIE PACKAGE INCLUDING ENCAPSULATED DIE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized. | 12-23-2010 |
20110042799 | DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die. | 02-24-2011 |
20110097856 | METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - Disclosed is a method of manufacturing a wafer level package, which includes arranging semiconductor dies on a carrier, forming a protective layer between the semiconductor dies of the carrier through screen printing, primarily heat hardening the protective layer, simultaneously pressing and secondarily heat hardening the protective layer, and removing the carrier, so that a thickness difference between the semiconductor dies and the protective layer is not formed and the warping of the wafer level package is reduced. | 04-28-2011 |
20130139753 | APPARATUS FOR MANUFACTURING SUBSTRATE - Disclosed herein is an apparatus for manufacturing a substrate. The apparatus for manufacturing a substrate includes: a reaction gas ejector ejecting reaction gas; a lift pin supporting the substrate and having a header contacting a rear surface of the substrate; and a support chuck having a lift pin insertion unit inserted with the lift pin and moving vertically and including a ring in a header insertion portion into which the header is inserted in the lift pin insertion unit. | 06-06-2013 |
20130319734 | PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a package substrate including: a base substrate; insulation layers formed on upper and lower portions of the base substrate; a first metal layer formed on an upper portion of the insulation layer; a first through-via penetrating through the base substrate, the insulation layer, and the first metal layer and being made of an insulating material; a seed layer formed on upper and lower portions and an inner wall of the first through-via; a second metal layer formed on upper portions of the first metal layer and the seed layer; and a second through-via formed in the seed layer formed at the inner wall of the first through-via and the second metal layer. | 12-05-2013 |
Patent application number | Description | Published |
20080211083 | Electronic package and manufacturing method thereof - An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being formed in the other surface of the second chip; encapsulating the second chip by coating the other surface of the PCB with an insulation material; and processing a first via by punching a hole on the insulation material, the first via being electrically interconnected to the pad, can perform stable handling in a process of mounting a semiconductor chip, make it unnecessary to add a process for chip encapsulation and realize a system in package having high density and high reliability. | 09-04-2008 |
20080212288 | Electronic component package and manufacturing method thereof - An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side. | 09-04-2008 |
20090087951 | Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased. | 04-02-2009 |
20090124075 | Method of manufacturing a wafer level package - A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved. | 05-14-2009 |
20090321118 | Printed circuit board embedded chip and manufacturing method thereof - An electronic component embedded printed circuit board and a manufacturing method thereof. The electronic component embedded printed circuit board includes an insulating layer forming a core layer; an electronic component inserted to project a part thereof on an upper part of the insulating layer; a metallic seed layer formed on the insulating layer including a projected surface of the electronic component; a plating layer formed on the metallic seed layer; circuit patterns electrically connected to pads of the electronic component through via-holes formed on the insulating layer; and a solder resist layer which is formed on the insulating layer and has solder balls attached onto the via-holes electrically connected to the circuit patterns. In the electronic component embedded printed circuit board, a heat radiation characteristic can be maximized and a thickness of the printed circuit board can be minimized. In case that the insulating is made of a thermoplastic resin, the electronic component can be reutilized, thereby saving product cost. | 12-31-2009 |
20100059881 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. The semiconductor package in accordance with an embodiment of the present invention includes: a substrate, in which a conductive pattern formed on one surface of the substrate; an insulation layer, which is formed on one surface of the substrate, in which a through-hole is formed in the insulation layer such that the conductive pattern is exposed; a metal post, which is formed in the through-hole such that one end of the metal post is in contact with the conductive pattern and the other end of the metal post is protruded from the insulation layer; and a solder bump, which is formed on the other end of the metal post. | 03-11-2010 |
20100133680 | Wafer level package and method of manufacturing the same and method of reusing chip - The present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip and provides a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding material formed on the lower surface of the removable resin layer; a dielectric layer formed over the removable resin layer including the chip and having via holes to expose portions of the chip; redistribution lines formed on the dielectric layer including insides of the via holes to be connected to the chip; and a solder resist layer formed on the dielectric layer to expose portions of the redistribution lines. Also, the present invention provides a method of manufacturing a wafer level package and a method of reusing a chip. | 06-03-2010 |
20100134991 | Chip embedded printed circuit board and manufacturing method thereof - The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The prevent invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof. | 06-03-2010 |
20110298102 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property. | 12-08-2011 |
20120042513 | Manufacturing method of printed circuit board embedded chip - A method of manufacturing an electronic component embedded printed circuit board including: mounting an electronic component on an insulating layer in a fluidal condition so that a part of the electronic component is inserted into the insulating layer and another part of the electronic component is protruded out of a top surface of the insulating layer by pressing the electronic component onto the insulating layer; fixing the electronic component by curing the insulating layer; forming a metallic seed layer on a top surface of the insulating layer including an exposed surface of the electronic component; forming a plating layer on the metallic seed layer; forming via-holes at positions on the insulating layer, which correspond to pads of the electronic component and forming circuit patterns electrically conducted with the pads; and forming a solder resist layer including the via-holes electrically connected to the circuit patterns. | 02-23-2012 |
20120129297 | METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines. | 05-24-2012 |
20140041906 | METAL HEAT RADIATION SUBSTRATE AND MANUFACTURING METHOD THEREOF - Disclosed herein are a metal heat radiation substrate and a manufacturing method thereof. The metal heat radiation substrate includes: a metal substrate having a through-hole formed therein; a heat resistant insulating material filled in the through-hole and having a via hole formed at a filled portion; a metal oxide film formed on upper and lower surfaces of the metal substrate except for an inner wall of the through-hole by performing anodizing thereon; and a conductive layer filled in the via hole and formed over the metal oxide film. | 02-13-2014 |
20140187112 | PREPREG, METHOD FOR MANUFACTURING THE SAME, AND COPPER CLAD LAMINATE USING THE SAME - Disclosed herein are a prepreg, including: an inorganic fiber, an organic fiber, or a hybrid fiber obtained by mix-weaving the inorganic fiber and the organic fiber, coated with a thermally conductive component or impregnated with a thermally conductive component; and a cross-linkable resin for impregnating the fiber therewith, a method for manufacturing the same, and a copper clad laminate using the same, so that the prepreg and the copper clad laminate can maintain a low coefficient of thermal expansion and a high modulus of elasticity and have excellent heat radiation property. | 07-03-2014 |
20140353004 | INSULATION RESIN COMPOSITION FOR PRINTED CIRCUIT BOARD HAVING IMPROVED THERMAL CONDUCTIVITY AND ELECTRICAL PROPERTIES, INSULATING FILM, PREPREG AND PRINTED CIRCUIT BOARD - Disclosed herein are an insulation resin composition for a printed circuit board including: an epoxy resin, a first inorganic filler having thermal conductivity of 20 W/mK or more, and a second inorganic filler having relative permittivity less than 10, and an insulating film, a prepreg, and a printed circuit board. | 12-04-2014 |
Patent application number | Description | Published |
20110108993 | Semiconductor package and manufacturing method thereof - There is provided a semiconductor package including: a circuit board having a receiving space formed therein; a semiconductor chip inserted into the receiving space of the circuit board; and an electrode pattern portion having a pattern shape on one surface of the semiconductor chip, and directly contacting a via portion of the circuit board so as to be electrically connected thereto. | 05-12-2011 |
20120295404 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board. | 11-22-2012 |
20130005089 | Wafer Level Package For Heat Dissipation And Method Of Manufacturing The Same - Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate. | 01-03-2013 |
20130056141 | DIE PACKAGE INCLUDING ENCAPSULATED DIE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized | 03-07-2013 |
20140054072 | PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a base substrate; an Insulating layer formed on one surface or both surfaces of the base substrate; an electrode layer formed on a top surface of the insulating layer; and an insulating film covering a surface of the insulating layer except for a bonding surface between the electrode layer and the insulating layer so as to secure high dielectric breakdown voltage while keeping high thermal conductivity. | 02-27-2014 |
20140174792 | INSULATING FILM FOR PRINTED CIRCUIT BOARD HAVING IMPROVED THERMAL CONDUCTIVITY, MANUFACTURING METHOD THEREOF, AND PRINTED CIRCUIT BOARD USING THE SAME - This invention relates to an insulating film for a printed circuit board having improved thermal conductivity, a manufacturing method thereof and a printed circuit board using the same, wherein the insulating film includes an amphiphilic block copolymer having a vertical structure formed in a thickness direction by chemically coupling a hydrophilic compound with a hydrophobic compound. | 06-26-2014 |
20140174794 | HEAT RADIATING SUBSTRATE AND MANUFACTURING METHOD THEREOF - A heat radiating substrate having strengthened insulation resistance and heat conductivity, and a manufacturing method thereof. The method for manufacturing a heat radiating substrate includes: preparing a metal substrate; performing an anodizing process on the metal substrate to form an anodic oxidation layer; filling surface pores of the anodic oxidation layer with an insulating material; and forming a metal wiring layer on the anodic oxidation layer. High insulation resistance and heat conductivity can be obtained by filling surface pores formed in an anodizing process with an insulating material. | 06-26-2014 |
20140187674 | RESIN COMPOSITION WITH ENHANCED HEAT-RELEASING PROPERTIES, HEAT-RELEASING FILM, INSULATING FILM, AND PREPREG - This invention relates to a resin composition with enhanced heat-releasing properties, including a liquid crystal oligomer, an epoxy resin, or a resin mixture thereof, and graphene oxide as a filler, and to a heat-releasing film for an electronic device, an insulating film for a printed circuit board, and a prepreg, which are manufactured using the resin composition. | 07-03-2014 |
20140313676 | ELECTRONIC COMPONENT PACKAGE - An electronic component package includes: a first insulation layer; an electronic component mounted in one surface of the first insulation layer; a heat sink formed with a cavity corresponding to the electronic component, bonded to the one surface of the first insulation layer to cover the electronic component, and formed with an inset hole and with an inlet hole; an adhesive charged in the cavity; and a circuit pattern formed in another surface of the first insulation layer. | 10-23-2014 |