Patent application number | Description | Published |
20080205136 | READ METHOD OF MEMORY DEVICE - A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a N | 08-28-2008 |
20080205138 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array. | 08-28-2008 |
20080205149 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device enables a pump in response to a first program confirm command. The pump generates a voltage. An initial page of a memory block is programmed. Subsequent intermediate pages of the memory block are programmed in response to a second program confirm command while the pump remains enabled. A final page of the memory block is programmed in response to a third program confirm command. The pump is then disabled after the final page is programmed. | 08-28-2008 |
20090097313 | PAGE BUFFER, MEMORY DEVICE HAVING THE PAGE BUFFER AND METHOD OF OPERATING THE SAME - A page buffer includes a first latch coupled between a sensing node and a data input/output node for storing data to be programmed. The sensing node is coupled to a bit line corresponding to an MLC selected for programming. The data input/output node receives/outputs data. A second latch is coupled to the sensing node for performing a program, verifying or read operation. A first switching means is coupled between the first latch and the sensing node for transmitting data stored in the first latch to the bit line through the sensing node when the program operation is performed. A second switching means is coupled to a first node of the second latch and the sensing node for verifying a first program operation. A third switching means is coupled between a second node of the second latch and the sensing node for verifying a second program operation. | 04-16-2009 |
20090122615 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Program voltages of a non-volatile memory device are controlled variably according to a program/erase operation count. The non-volatile memory device includes a program voltage supply unit for applying a program voltage to a memory cell, a program/erase count storage unit for storing a total program/erase operation count of the non-volatile memory device, a program start voltage storage unit for storing levels of program start voltages to be differently supplied according to the program/erase operation count, and a program voltage controller for controlling the program start voltage according to the program/erase operation count. | 05-14-2009 |
20090122616 | NON-VOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING A BULK VOLTAGE THEREOF - A threshold voltage of a non-volatile memory device is compensated by a voltage supplier and a controller. The voltage supplier supplies a set voltage to a bulk of a memory cell array, including memory cells, at the time of a read operation of the memory cells. The controller controls the voltage supplier to set and supply a bulk voltage depending on a threshold voltage change of the memory cells. | 05-14-2009 |
20090141560 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result. | 06-04-2009 |
20090141561 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved. | 06-04-2009 |
20090161443 | PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register. | 06-25-2009 |
20090161444 | PAGE BUFFER AND PROGRAMMING METHOD OF A NON-VOLATILE MEMORY DEVICE - A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node. | 06-25-2009 |
20090172482 | METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE - Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks. | 07-02-2009 |
20100284224 | FLASH MEMORY DEVICE AND ERASE METHOD USING THE SAME - A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated in response to the block control signals. | 11-11-2010 |
20100309727 | METHOD OF OPERATING MEMORY DEVICE HAVING PAGE BUFFER - A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage. | 12-09-2010 |
20110141809 | PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data. | 06-16-2011 |