Patent application number | Description | Published |
20090079001 | MULTI-CHANNEL ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode. | 03-26-2009 |
20090079022 | METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage. | 03-26-2009 |
20090162988 | METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage. | 06-25-2009 |
20100006889 | LOW CLAMP VOLTAGE ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode. | 01-14-2010 |
20100059815 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG AND METHOD - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 03-11-2010 |
20110021009 | LOW CLAMP VOLTAGE ESD METHOD - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode. | 01-27-2011 |
20110233635 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 09-29-2011 |
20130277807 | ELECTRONIC DEVICE INCLUDING A FEATURE IN AN OPENING - A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows. | 10-24-2013 |
20140251542 | WAFER SUSCEPTOR FOR FORMING A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, a wafer susceptor is formed to have portion of the susceptor that is positioned between a wafer pocket and an outside edge of the susceptor to have a non-uniform and/or a non-planar surface. In another embodiment, the non-uniform and/or non-planar surface includes one of a recess into the surface or a protrusion extending away from the surface. | 09-11-2014 |
20140264369 | HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device. | 09-18-2014 |
20140264449 | METHOD OF FORMING HEMT SEMICONDUCTOR DEVICES AND STRUCTURE THEREFOR - In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer. | 09-18-2014 |
20140264456 | METHOD OF FORMING A HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE - In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of SiC or a III-V series material on the base substrate. In a different embodiment, the base substrate may be one of silicon, porous silicon, or porous silicon with nucleation sites formed thereon, or silicon in a (111) plane. | 09-18-2014 |
20140264761 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 09-18-2014 |