Patent application number | Description | Published |
20140281778 | BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL - A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. | 09-18-2014 |
20150276866 | RESET GENERATION CIRCUIT FOR SCAN MODE EXIT - A reset generation circuit of an integrated circuit uses a scan data input pin as a scan mode exit control, which is enabled only when the IC reset pin of the device is active. The reset generation circuit allows a TAP controller to be scan testable yet at the same time the circuit provides a method to exit scan mode without requiring a power-up sequence or an extra pin. | 10-01-2015 |
20150285859 | INTEGRATED CIRCUIT WITH LBIST SUB-PARTITIONS - A Logic Built-In Self-Test (LBIST) domain of an integrated circuit is divided into partitions that in turn are subdivided into sub-partitions. Each sub-partition has an associated clock gating logic circuit that enables or inhibits the clock signal supplied to scan chains within the sub-partition. A user-defined number of sub-partitions, which can be specified on the basis of silicon results and power requirements of the integrated circuit, may be activated at any one time during a portion of an LBIST execution, which reduces toggling of concurrent scan chains, resulting in a reduction of energy consumption during testing, and reduces voltage droop due to inertia of power management control modules at the start of an LBIST test. | 10-08-2015 |
Patent application number | Description | Published |
20120027159 | SYSTEM AND METHOD FOR SETTING COUNTER THRESHOLD VALUE - A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A frequency sub-range of the reference clock signal is determined using the frequency sub-range control signals and the determined frequency sub-range is used to select a counter threshold value. The selected counter threshold value is provided to a counter and the counter then is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value. | 02-02-2012 |
20120192021 | METHOD OF TESTING ASYNCHRONOUS MODULES IN SEMICONDUCTOR DEVICE - A method of testing a semiconductor device that includes first and second mutually asynchronous modules, a buffer for storing transaction data for read/write operations from the first module and transferring it to the second module synchronously with the data rate of the second module, and an inhibit input. The second module receives the transaction data from the buffer and transfers the data to a data output when the inhibit signal is de-asserted and not when the inhibit signal is asserted. The method of testing includes repeatedly: asserting the inhibit signal; providing test transaction data to the first module and storing the data in the buffer while the inhibit signal is asserted; de-asserting the inhibit signal so that the second module transfers test transaction data received from the buffer to the data output synchronously with the data rate of the second module; and capturing deterministically test transaction data from the output of the second module. | 07-26-2012 |
20120278027 | SYSTEM FOR PERFORMING ELECTRICAL CHARACTERIZATION OF ASYNCHRONOUS INTEGRATED CIRCUIT INTERFACES - An integrated circuit with a single-channel input/output (I/O) interface and a multi-channel I/O interface includes functional circuits that operate in different clock domains and a test circuit. For a single-channel I/O interface, the test circuit simulates read/write operations by bypassing the functional circuits and performs electrical characterization of the single-channel I/O interface. For a multi-channel I/O interface, the test circuit configures a plurality of channels of the multi-channel interface in a half-duplex mode and performs electrical characterization using data loop back by bypassing the functional circuits. | 11-01-2012 |
20130218508 | SYSTEM FOR TESTING ELECTRONIC CIRCUITS - A system for testing electronic circuits includes first, second, and third standard interfaces. A test port master and a test port slave are connected to an external testing apparatus. The first, second, and third standard interfaces are tested in first, second, and third test modes, respectively. The tests are initiated by asserting a test mode activate and first, second, and third test mode enable signals, respectively, which enable reuse of test patterns across different electronic circuits. | 08-22-2013 |
20150348648 | APPARATUS FOR MEASURING SIGNAL SKEW OF ASYNCHRONOUS FLASH MEMORY CONTROLLER - A method of measuring skew between signals from an asynchronous integrated flash memory controller (IFC) includes connecting input/output (I/O) pins of the IFC to cycle based test equipment (ATE). The ATE applies a pattern of test signals as input drive to the IFC. Relative to the test cycle, the earliest delay time at which output signals from all of the I/O pins first correspond with expected results, and the latest delay time at which the output signals still correspond with the expected results are measured. The difference between the latest and the earliest delay times is compared with a limit value and a comparison report is generated. | 12-03-2015 |
Patent application number | Description | Published |
20100254251 | ARTICLES INVOLVING ENCAPSULATION OF HYGROSCOPIC MATERIALS - An article involving encapsulation of one or more hygroscopic materials and manufacturing method and system thereof are provided. The article includes a first substrate, a second substrate, one or more first structures formed at a first periphery associated with the first substrate, and one or more second structures formed at a second periphery associated with the second substrate. The first structures and the second structures are engaged together mechanically to form an enclosure between the first substrate and the second substrate. The enclosure is capable of preventing exposure of a hygroscopic material encapsulated between the first substrate and the second substrate to the surrounding environment. | 10-07-2010 |
20110195533 | METHOD OF MANUFACTURING ORGANIC LIGHTING DEVICE - A method of manufacturing an organic lighting device, having a form factor substantially equal to or less than 900 square centimeters, without involving a cutting process is provided. The method includes providing one or more first substrates with a size substantially equal to the form factor. Thereafter, the method includes a high throughput first processing of the one or more first substrates and active layer deposition processing on the one or more first substrates. Further, one or more second substrates having a size substantially equal or less than the form factor are provided. Thereafter, a high throughput second processing is performed on the one or more second substrates. Finally, the method includes encapsulating at least one of the one or more first substrates with at least one of the one or more second substrates to form the organic lighting device having the form factor. | 08-11-2011 |
20120208312 | METHOD OF MANUFACTURING ORGANIC PHOTOVOLTAIC DEVICE - A method of manufacturing an organic photovoltaic device of a pre-defined shape and size is provided. The method includes providing a first substrate with said pre-defined shape and size, the size being less than 900 square centimeters and depositing an organic photoactive layer on said first substrate followed by depositing an electrically conducting layer on said organic photoactive layer. Thereafter, said electrically conducting layer and said organic photoactive layer are scribed from said first substrate forming zones on first substrates, whereby forming an active substrate. Further, providing a second substrate with said pre-defined shape and size and depositing a gas-absorbent layer on said second substrate whereby forming an inactive substrate. Finally, encapsulating said active substrate with said inactive substrate to form said organic photovoltaic device with said pre-defined shape and size, whereby not involving cutting of said first substrate after deposition of said organic photoactive layer. | 08-16-2012 |
Patent application number | Description | Published |
20090070100 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR SPOKEN LANGUAGE GRAMMAR EVALUATION - A method, system, and computer program product for spoken language grammar evaluation are provided. The method includes playing a recorded question to a candidate, recording a spoken answer from the candidate, and converting the spoken answer into text. The method further includes comparing the text to a grammar database, calculating a spoken language grammar evaluation score based on the comparison, and outputting the spoken language grammar evaluation score. | 03-12-2009 |
20090070111 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR SPOKEN LANGUAGE GRAMMAR EVALUATION - A method, system, and computer program product for spoken language grammar evaluation are provided. The method includes playing a recorded question to a candidate, recording a spoken answer from the candidate, and converting the spoken answer into text. The method further includes comparing the text to a grammar database, calculating a spoken language grammar evaluation score based on the comparison, and outputting the spoken language grammar evaluation score. | 03-12-2009 |
Patent application number | Description | Published |
20120238264 | METHOD AND APPARATUS TO SUPPORT SEAMLESS MOBILITY ACROSS OFFLOAD GATEWAYS - A method is described that involves performing the following at an offload network gateway: receiving a RELOCATION_REQUIRED message from an RNC; recognizing that the RELOCATION | 09-20-2012 |
20130097674 | METHODS AND APPARATUSES TO PROVIDE SECURE COMMUNICATION BETWEEN AN UNTRUSTED WIRELESS ACCESS NETWORK AND A TRUSTED CONTROLLED NETWORK - A request for an IP address for a client device having a first identifier information is received from an AP device. The request for the IP address is associated with a first communication protocol. The first identifier information is compared to a second identifier information. The second identifier information is associated with a second communication protocol. The second communication protocol is different from the first communication protocol. The IP address for the client device based on comparing. | 04-18-2013 |
20140050208 | APN IP MANAGEMENT - In one embodiment, a WLAN gateway (WGW) receives a dynamic host configuration protocol (DHCP) request from a WLAN controller for an IP address of a user equipment (UE). In one embodiment, DHCP server within the WGW assigns a local IP (LIP) address to the UE from a pool of local IP addresses maintained by the DHCP server. The WGW communicates the UE LIP address to the WLAN controller, wherein the UE LIP address is used by the WLAN controller to identify traffic to/from the UE while the UE is communicatively coupled to the WLAN and exchange the DE traffic between WGW and WLAN controller. In one embodiment, the WGW is configured to perform network address translation between the UE LIP and an external IP address assigned by one or more networks of the mobile network operator (MNO) to allow the UE to reach the network(s) in addition to the Internet. | 02-20-2014 |
20140126532 | SEAMLESS MOBILITY FROM 3G NETWORK TO WIFI NETWORK - According to one aspect, a multi-function gateway device (MFG) receives a request for terminating a first data session identified by a first IP address, the request originating either directly from a user equipment (UE), or indirectly from the UE via a radio access controller (RNC), wherein the UE is communicatively coupled to a 3G radio access network (RAN), such that data traffic of the first data session is routed to a first serving GPRS support node (SGSN). According to one aspect of the invention, the MFG further determines whether the UE is connected to the MFG via a WiFi RAN, any 3G call teardown related messages are blocked in order to keep the 3G GTP-U tunnel up. Continue routing user's data originating via the WiFi RAN over the GTP-U tunnel with the SGSN. | 05-08-2014 |