Patent application number | Description | Published |
20150035018 | DEVICES AND METHODS OF FORMING BULK FINFETS WITH LATERAL SEG FOR SOURCE AND DRAIN ON DIELECTRICS - Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer. | 02-05-2015 |
20150069515 | INTEGRATED CIRCUITS HAVING LATERALLY CONFINED EPITAXIAL MATERIAL OVERLYING FIN STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction. | 03-12-2015 |
20150091094 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 04-02-2015 |
20150104918 | FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS - Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges. | 04-16-2015 |
20150123250 | METHODS OF FABRICATING DEFECT-FREE SEMICONDUCTOR STRUCTURES - Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure. | 05-07-2015 |
20150194307 | STRAINED FIN STRUCTURES AND METHODS OF FABRICATION - Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material. The resultant device may have tensile strained fin structures or compressively strained fin structures, or both. | 07-09-2015 |
20150214330 | REPLACEMENT LOW-K SPACER - A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer. | 07-30-2015 |
20150243563 | INTEGRATED CIRCUIT HAVING MULTIPLE THRESHOLD VOLTAGES - In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack. | 08-27-2015 |
20150243652 | INTEGRATION METHOD FOR FABRICATION OF METAL GATE BASED MULTIPLE THRESHOLD VOLTAGE DEVICES AND CIRCUITS - In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage. | 08-27-2015 |