Patent application number | Description | Published |
20090031153 | Power Management Server for Managing Power Consumption - A power management server and method for managing power consumption is disclosed. According to one embodiment, a power management server data processing system is provided, where the power management server data processing system comprises a power management communication port to communicatively couple the power management server data processing system to a power-managed server data processing system and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises power management logic configured to receive power management data from the power-managed server data processing system, to generate a power management command utilizing the power management data, and to transmit the power management command to the power-managed server data processing system utilizing the power management communication port. Moreover, the power management data of the described embodiment comprises power management capability data. | 01-29-2009 |
20090091186 | SYSTEM AND METHOD FOR MULTIPLE SENSE POINT VOLTAGE REGULATION - The present invention is a system and method for sensing the voltage at multiple sense points. The present invention acquires optimal feedback from a plurality of sources including those integrated on the same motherboard, for populated or unpopulated connectors and for adapter cards plugged into the connectors, for the purpose of controlling the voltage regulator output. The voltage regulator, connected to a logic system, provides voltage to those connectors needing the voltage. | 04-09-2009 |
20090157920 | Dynamically Allocating Communication Lanes For A Plurality Of Input/Output ('I/O') Adapter Sockets In A Point-To-Point, Serial I/O Expansion Subsystem Of A Computing System - Methods, systems, and products are disclosed for dynamically allocating communication lanes for a plurality of sockets in a point-to-point, serial I/O expansion subsystem of a computing system, the expansion subsystem including an switch that supports a maximum number of enabled communication lanes, each socket having a same form factor, each socket connected to the switch using a same predefined number of communication lanes, that include: identifying, during a boot process for the computing system, each of the sockets in which an adapter is installed; determining, for each installed adapter, a maximum link width for that adapter; and enabling, for each of the sockets in which an adapter is installed, a set of communication lanes for communications between the adapter installed in that socket and the expansion subsystem switch in dependence upon the maximum link width for each adapter and the maximum number of enabled communication lanes supported by the switch. | 06-18-2009 |
20090164846 | Fault Injection In Dynamic Random Access Memory Modules For Performing Built-In Self-Tests - Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module. | 06-25-2009 |
20100293410 | Memory Downsizing In A Computer Memory Subsystem - Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs. | 11-18-2010 |
20110080700 | Airflow Barriers for Efficient Cooling of Memory Modules - Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load. | 04-07-2011 |
20110160916 | Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack - Computing devices have fan speeds governing airflows through the computing devices. The rack has a maximum airflow associated with a cooling component for the rack. The computing devices transmit their current airflows. A sum of the current airflows is determined. Where the sum is greater than the maximum airflow, the fan speeds of one or more selected computing devices are decreased. The fan speeds of lower priority computing devices may be reduced before the fan speeds higher priority computing devices are reduced. Fan speed reduction may be achieved in a centralized manner, by employing a centralized management component, or in a decentralized manner, without employing a centralized management component. | 06-30-2011 |
20110192577 | Heat Sink For Dissipating A Thermal Load - A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink. | 08-11-2011 |
20120173653 | VIRTUAL MACHINE MIGRATION IN FABRIC ATTACHED MEMORY - A computer program product and computer implemented method are provided for migrating a virtual machine between servers. The virtual machine is initially operated on a first server, wherein the first server accesses the virtual machine image over a network at a memory location within fabric attached memory. The virtual machine is migrated from the first server to a second server by flushing data to the virtual machine image from cache memory associated with the virtual machine on the first server and providing the state and memory location of the virtual machine to the second server. The virtual machine may then operate on the second server, wherein the second server accesses the virtual machine image over the network at the same memory location within the fabric attached memory without copying the virtual machine image. | 07-05-2012 |
20120199337 | Heat Sink for Dissipating a Thermal Load - A heat sink for dissipating a thermal load is disclosed that includes one or more heat sink bases configured around a central axis of the heat sink so as to define an interior space, at least one heat sink base receiving the thermal load, a thermal transport connected to the at least one heat sink base receiving the thermal load so as to distribute the thermal load in the heat sink, and heat-dissipating fins connected to each heat sink base, the heat-dissipating fins extending from each heat sink base into the interior space of the heat sink, each heat-dissipating fin shaped according to the location of the heat-dissipating fin with respect to the location of the thermal load and the location of the distributed thermal load in the heat sink. | 08-09-2012 |
20120218024 | Integrated Circuit Die Stacks With Translationally Compatible Vias - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die. | 08-30-2012 |
20120286431 | Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Switches - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die. | 11-15-2012 |
20120299640 | Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Fuses - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die. | 11-29-2012 |
20130019048 | Memory Access To A Dual In-line Memory Module Form Factor Flash MemoryAANM Bland; Patrick M.AACI RaleighAAST NCAACO USAAGP Bland; Patrick M. Raleigh NC USAANM Desai; Dhruv M.AACI CaryAAST NCAACO USAAGP Desai; Dhruv M. Cary NC USAANM Foster, SR.; Jimmy G.AACI MorrisvilleAAST NCAACO USAAGP Foster, SR.; Jimmy G. Morrisville NC USAANM Ono; MakotoAACI CaryAAST NCAACO USAAGP Ono; Makoto Cary NC US - Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller. | 01-17-2013 |
20130159687 | Memory Training Results Corresponding To A Plurality Of Memory Modules - Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system. | 06-20-2013 |
20130214855 | Integrated Circuit Die Stacks With Rotationally Symmetric VIAS - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die. | 08-22-2013 |
20140098480 | MEMORY MODULE CONNECTOR WITH AUXILIARY POWER CABLE - A memory module includes persistent-storage memory chips and an auxiliary voltage connector for powering the persistent-storage memory chips. An auxiliary power cable has a first end coupled to an electronic power source on the system board and has a second end having connector that plugs in to the auxiliary voltage connector on the memory module to provide power to the persistent-storage memory chips. The auxiliary power cable also resists movement of a latch lever to require disconnecting the auxiliary power cable before ejecting the memory module. | 04-10-2014 |
20140099815 | MEMORY MODULE CONNECTOR WITH AUXILIARY POWER - An apparatus includes a socket that receives a memory module that includes a card having card edge voltage pads along the lower card edge, auxiliary voltage pads along at least one of the vertical card edges, and one or more persistent, solid-state memory chips on one or both card faces. A latch pivotally coupled to the socket is movable between a latched position and an unlatched position. The latch includes electrical latch contacts positioned for being engaged with the auxiliary voltage pads when that latch is in the latched position and being disengaged from the auxiliary voltage pads when the latch is in the unlatched position. The electrical latch contacts may provide a different voltage to the auxiliary voltage pads than the socket provides to the card edge voltage pads along the lower card edge. | 04-10-2014 |
20140189164 | MEMORY BUS ATTACHED INPUT/OUTPUT ('I/O') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM - Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests. | 07-03-2014 |
20140189186 | MEMORY BUS ATTACHED INPUT/OUTPUT ('I/O') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM - Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests. | 07-03-2014 |