Patent application number | Description | Published |
20140203445 | MITIGATING PATTERN COLLAPSE - One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example. | 07-24-2014 |
20140252625 | Method of Preventing a Pattern Collapse - A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric. | 09-11-2014 |
20140252636 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap. | 09-11-2014 |
20140252648 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a first metal line and a second metal line over a substrate; a portion of a first low-k (LK) dielectric layer between the first metal line and the second metal line; and a second LK dielectric layer over the portion of the first LK dielectric layer. A top surface of the second LK dielectric layer is substantially coplanar with a top surface of the first metal line or the second metal line, and a thickness of the second LK dielectric layer is less than a thickness of the first metal line or a thickness of the second metal line. | 09-11-2014 |
20140256155 | Cleaning Solution for Preventing Pattern Collapse - A chemical solution for use in cleaning a patterned substrate includes water, from approximate 0.01 to 99.98 percent by weight; hydrogen peroxide, from 0 to 30 percent by weight; a pH buffering agent, from approximate 0.01 to 50 percent by weight; a metal chelating agent, from approximate 0 to 10 percent by weight; and a compound for lowering a surface tension of the combination of water, hydrogen peroxide, pH buffering agent, and metal chelating agent. Examples of the compound include an organic solvent, from approximate 0 to 95 percent by weight, or a non-ionic surfactant agent, from approximate 0 to 2 percent by weight. | 09-11-2014 |
20140264903 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap. | 09-18-2014 |
20150024588 | Hard Mask Removal Scheme - A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is located through the dielectric layer and the hard mask layer. A filler layer is formed in the via hole and over the barrier layer. The filler layer and the hard mask layer are removed. A metal layer is formed in the via hole. | 01-22-2015 |
20150348834 | Hard Mask Removal Scheme - A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is located through the dielectric layer and the hard mask layer. A filler layer is formed in the via hole and over the barrier layer. The filler layer and the hard mask layer are removed. A metal layer is formed in the via hole. | 12-03-2015 |