Patent application number | Description | Published |
20130065328 | FOCUS CONTROL METHOD FOR PHOTOLITHOGRAPHY - A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process. | 03-14-2013 |
20130069162 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 03-21-2013 |
20130071957 | System and Methods for Semiconductor Device Performance Prediction During Processing - Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described. | 03-21-2013 |
20130221353 | Methods and Apparatus for Testing Pads on Wafers - Methods and apparatuses for sharing test pads among function blocks under test within multiple layers of a die are disclosed. A semiconductor wafer comprises a first die and a second die separated by a scribe line. A first pad, a second pad, and a third pad are located in the scribe line. The test pads may be located within a die as well. The first pad and the second pad are used to test a first function block within a first layer, and the first pad and the third pad are used to test a second function block within a second layer of the first die. The shared first test pad are used to test multiple function blocks contained in different layers of the die. Therefore fewer test pads are needed which leads to reduced area for scribe lines in a wafer. | 08-29-2013 |
20130244139 | Reflective Lithography Masks and Systems and Methods - Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed. | 09-19-2013 |
20130244140 | Non-Planar Lithography Mask and System and Methods - Various non-planar lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a lens-type transparent substrate and a reticle pattern on a surface of the lens-type transparent substrate. The reticle pattern is opaque to optical radiation. Methods for forming similar lithography masks and for using similar lithography masks are disclosed. | 09-19-2013 |
20130285194 | OPTICAL PROXIMITY CORRECTION FOR ACTIVE REGION DESIGN LAYOUT - The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature. | 10-31-2013 |
20140021552 | Strain Adjustment in the Formation of MOS Devices - A method includes forming a gate stack over a semiconductor substrate, and forming a gate spacer on a sidewall of the gate stack. After the step of forming the gate spacer, the gate spacer is etched to reduce a thickness of the gate spacer. A strained layer is then formed. The strained layer includes a portion on an outer sidewall of the gate spacer, and a portion over the gate stack. | 01-23-2014 |
20140117467 | Metal-Oxide-Semiconductor Field-Effect Transistor with Spacer over Gate - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode. | 05-01-2014 |
20140239363 | CAPACITORS COMPRISING SLOT CONTACT PLUGS AND METHODS OF FORMING THE SAME - An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An Inter-Layer Dielectric (ILD) is overlying the insulation region. A capacitor includes a first capacitor plate including a first slot contact plug, and a second capacitor plate including a second slot contact plug. The first and the second contact plugs include portions in the ILD. A portion of the ILD between vertical surfaces of the first slot contact plug and the second slot contact plug acts as a capacitor insulator of the capacitor. | 08-28-2014 |
20140252549 | Metal-Insulator-Metal Capacitor - An embodiment metal-insulator-metal (MiM) capacitor includes a gate stack disposed upon an insulation layer, the gate stack including a gate metal, the gate metal serving as a bottom electrode, a dielectric layer disposed upon the gate stack, and a top metal layer disposed upon the dielectric layer, the top metal serving as a top electrode. | 09-11-2014 |
20140264743 | NOVEL STRUCTURE OF METAL GATE MIM - First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film. | 09-18-2014 |
20140264750 | Resistor and Metal-Insulator-Metal Capacitor Structure and Method - A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the circuit device comprises a substrate and a passive device disposed on the substrate. The passive device includes a bottom plate disposed over the substrate, a top plate disposed over the bottom plate, a spacing dielectric disposed between the bottom plate and the top plate, a first contact and a second contact electrically coupled to the top plate, and a third contact electrically coupled to the bottom plate. The passive device is configured to provide a target capacitance and a first target resistance. The passive device may also include a second top plate disposed over the bottom plate and configured to provide a second target resistance, such that the second target resistance is different from the first target resistance. | 09-18-2014 |
20140293250 | FOCUS CONTROL APPARATUS FOR PHOTOLITHOGRAPHY - A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process. | 10-02-2014 |
20140333914 | Reflective Lithography Masks and Systems and Methods - Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed. | 11-13-2014 |