Patent application number | Description | Published |
20110041017 | On-Die Logic Analyzer For Semiconductor Die - In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed. | 02-17-2011 |
20120131404 | Providing An On-Die Logic Analyzer (ODLA) Having Reduced Communications - In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed. | 05-24-2012 |
20130054931 | On-Die Logic Analyzer For Semiconductor Die - In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed. | 02-28-2013 |
20130103987 | On-Die Logic Analyzer For Semiconductor Die - In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed. | 04-25-2013 |
20140053026 | ON-DIE LOGIC ANALYZER FOR SEMICONDUCTOR DIE - In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed. | 02-20-2014 |
20140253221 | On-Die Programmable Fuses - In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used. | 09-11-2014 |
20140254233 | Redundant Fuse Coding - In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array. | 09-11-2014 |
20140254234 | RANDOM FUSE SENSING - In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device. | 09-11-2014 |
20140254296 | Bit Based Fuse Repair - In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output. | 09-11-2014 |
20140283119 | Tiered Access to On Chip Features - In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access. | 09-18-2014 |