Patent application number | Description | Published |
20100200991 | Dopant Enhanced Interconnect - Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved. | 08-12-2010 |
20120161295 | CYCLIC CARBOSILANE DIELECTRIC FILMS - Embodiments of the invention provide dielectric films and low-k dielectric films and methods for making dielectric and low-k dielectric films. Dielectric films are made from carbosilane-containing precursors. In embodiments of the invention, dielectric film precursors comprise attached porogen molecules. In further embodiments, dielectric films have nanometer-dimensioned pores. | 06-28-2012 |
20130249049 | CYCLIC CARBOSILANE DIELECTRIC FILMS - Embodiments of the invention provide dielectric films and low-k dielectric films and methods for making dielectric and low-k dielectric films. Dielectric films are made from carbosilane-containing precursors. In embodiments of the invention, dielectric film precursors comprise attached porogen molecules. In further embodiments, dielectric films have nanometer-dimensioned pores. | 09-26-2013 |
20130320520 | CHEMICALLY ALTERED CARBOSILANES FOR PORE SEALING APPLICATIONS - A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; and forming a film including the molecule. An apparatus including a circuit substrate including a plurality of devices; a plurality of interconnect lines disposed in a plurality of layers coupled to the plurality of devices; and a plurality of dielectric layers disposed between the plurality of interconnect lines, wherein at least one of the dielectric layers comprises a porous material surface relative to the plurality of devices and the surface comprises a pore obstructing material. | 12-05-2013 |
20140029181 | INTERLAYER INTERCONNECTS AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards interlayer interconnects and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, one or more device layers disposed on the semiconductor substrate, and one or more interconnect layers disposed on the one or more device layers, the one or more interconnect layers including interconnect structures configured to route electrical signals to or from the one or more device layers, the interconnect structures comprising copper (Cu) and germanium (Ge). Other embodiments may be described and/or claimed. | 01-30-2014 |
20140091467 | FORMING BARRIER WALLS, CAPPING, OR ALLOYS /COMPOUNDS WITHIN METAL LINES - Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits. | 04-03-2014 |
20140183738 | COBALT BASED INTERCONNECTS AND METHODS OF FABRICATION THEREOF - A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect comprising cobalt includes a dielectric layer disposed on a substrate, an opening formed in the dielectric layer such that the substrate is exposed. The embodiment further includes a seed layer disposed over the substrate and a fill material comprising cobalt formed within the opening and on a surface of the seed layer. | 07-03-2014 |
20150084198 | INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES - A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1. | 03-26-2015 |