Patent application number | Description | Published |
20110298132 | ULTRA-LOW POWER SWNT INTERCONNECTS FOR SUB-THRESHOLD CIRCUITS - Ultra-low power single metallic single-wall-nano-tube (SWNT) interconnects for sub-threshold circuits are provided. According to some embodiments, an interconnect structure for use in electronic circuits can generally comprise a first substrate, a second substrate, and an interconnect. The first substrate can be spaced apart from the second substrate. The interconnect is preferably a single wall carbon nanotube (SWNT) interconnect. The SWNT interconnect can be disposed between the first and second substrates to electrically connect the substrates. The substrates can form parts of electrical components (e.g., a transistor, processor, memory, filters, etc.) operating in a subthreshold operational state. Other aspects, features, and embodiments are claimed and described. | 12-08-2011 |
20140080255 | ULTRA-LOW POWER SWNT INTERCONNECTS FOR SUB-THRESHOLD CIRCUITS - Ultra-low power single metallic single-wall-nano-tube (SWNT) interconnects for sub-threshold circuits are provided. According to some embodiments, an interconnect structure for use in electronic circuits can generally comprise a first substrate, a second substrate, and an interconnect. The first substrate can be spaced apart from the second substrate. The interconnect is preferably a single wall carbon nanotube (SWNT) interconnect. The SWNT interconnect can be disposed between the first and second substrates to electrically connect the substrates. The substrates can form parts of electrical components (e.g., a transistor, processor, memory, filters, etc.) operating in a subthreshold operational state. Other aspects, features, and embodiments are claimed and described. | 03-20-2014 |
Patent application number | Description | Published |
20090012855 | SYSTEM AND METHOD OF USING CAPTCHAS AS ADS - A method of using advertisements in a Completely Automatic Public Turing test to tell Computers and Humans Apart (CAPTCHA) challenge/response transaction. In accordance with one aspect, a server allows access to some resource if the response to the ad/CAPTCHA challenge is an acceptable response. | 01-08-2009 |
20100076922 | DETECTING BULK FRAUDULENT REGISTRATION OF EMAIL ACCOUNTS - The invention provides for at least three processes for detecting the probability of abusive use of a message account for sending large amounts of unsolicited messages, such as spam, to other message accounts. For example, information provided at registration for a new message account can be processed to determine the likelihood of abusive use of that message account. Also, inbound messages can be processed to determine if the message account that sent the inbound message is abusing the use of that message account. Additionally, outbound messages can be processed to determine if the message account that is attempting to send an outbound message is abusing the use of that message account. Each of these three processes can operate separately or in any combination with each other to further improve the probability that abusive use of a message account will be detected promptly and accurately. | 03-25-2010 |
20100077040 | DETECTION OF OUTBOUND SENDING OF SPAM - The invention provides for at least three processes for detecting the probability of abusive use of a message account for sending large amounts of unsolicited messages, such as spam, to other message accounts. For example, information provided at registration for a new message account can be processed to determine the likelihood of abusive use of that message account. Also, inbound messages can be processed to determine if the message account that sent the inbound message is abusing the use of that message account. Additionally, outbound messages can be processed to determine if the message account that is attempting to send an outbound message is abusing the use of that message account. Each of these three processes can operate separately or in any combination with each other to further improve the probability that abusive use of a message account will be detected promptly and accurately. | 03-25-2010 |
20130226908 | DETECTION AND PREVENTION OF UNWANTED CONTENT ON CLOUD-HOSTED SERVICES - The problem of abuse of privileges at cloud-hosted service sites is addressed by connecting a single individual or “actor” with multiple user accounts and/or other online identities, thereby creating a “consolidated profile.” In this way a confidence level can be established that a particular user account, IP address or other identifying attribute is associated with a particular actor. Different confidence levels may suffice depending on the remediary action to be taken; for example, holding a message for human review is obviously less draconian than rejecting the actor's registration at sign-up, and would therefore require a lower degree of confidence. | 08-29-2013 |
20130226938 | DETECTION AND PREVENTION OF UNWANTED CONTENT ON CLOUD-HOSTED SERVICES - The problem of abuse of privileges at cloud-hosted service sites is addressed by associating each user, preferably across multiple cloud-hosted service sites, with an individual “suspiciousness” score that may vary over time as additional user actions are detected and evaluated. Knowledge of the user is employed to better analyze the appropriateness or acceptability of user actions on the site. | 08-29-2013 |
20130227016 | DETECTION AND PREVENTION OF UNWANTED CONTENT ON CLOUD-HOSTED SERVICES - The problem of abuse of privileges at cloud-hosted service sites is addressed at the sign-up stage by identifying suspicious or abusive users and preventing them from signing up in the first place. This approach may utilize a relatively small initial data set based on the recognition that while abusers' profiles are mutable and difficult to characterize stably abusers will deliberately shift their usage patterns to evade detection—a site's legitimate users tend to have similar and stable characteristics; that is, such characteristics are “cohesive” across cloud-hosted service (e.g., social media) sites and their users. The information gleaned from analysis of this small data set can be applied to a much larger, unsorted data set to obtain profiling criteria based on a large population for statistical reliability. | 08-29-2013 |
Patent application number | Description | Published |
20110204724 | Dual Output Direct Current (DC)-DC Regulator - An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output. | 08-25-2011 |
20120098570 | PLL DUAL EDGE LOCK DETECTOR - A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. | 04-26-2012 |
20120098609 | Crystal Oscillator With Low-Power Mode - Circuits having corresponding methods and computer-readable media comprise: an amplifier; a crystal port configured to be electrically coupled to a crystal, wherein a first terminal of the crystal port is electrically coupled to an input of the amplifier, and wherein a second terminal of the crystal port is electrically coupled to an output of the amplifier; a first capacitor, wherein a first terminal of the first capacitor is electrically coupled to ground; a second capacitor, wherein a first terminal of the second capacitor is electrically coupled to ground; a first switch configured to selectively electrically couple the input of the amplifier to a second terminal of the first capacitor; and a second switch configured to selectively electrically couple the output of the amplifier to a second terminal of the second capacitor. | 04-26-2012 |
20140071721 | VOLTAGE REGULATOR AND METHOD FOR REGULATING DUAL OUTPUT VOLTAGES BY SELECTIVE CONNECTION BETWEEN A VOLTAGE SUPPLY AND MULTIPLE CAPACITANCES - A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage. | 03-13-2014 |
Patent application number | Description | Published |
20120286393 | FINGER METAL OXIDE METAL CAPACITOR STRUCTURES - A finger metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit. First and second side portions include a plurality of first and second finger sections extending in the plurality of metal layers and first and second hole vias connecting the first and second finger sections, respectively. A middle portion connects the first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. A plurality of “T”-shaped sections are defined in the plurality of metal layers and third hole vias connecting the plurality of “T”-shaped sections. Middle portions of the plurality of “T”-shaped sections extend towards the middle portion and between the first side portion and the second side portion of the outer conducting structure. | 11-15-2012 |
20130307596 | PLL DUAL EDGE LOCK DETECTOR - A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. | 11-21-2013 |
20130321378 | PIXEL LEAKAGE COMPENSATION - A display system has a display panel in which there are a first subset of pixels and a second subset of pixels. A first common voltage generation circuit drives a first common voltage line that is coupled to the first subset, and a second common voltage generation circuit drives a second common voltage line that is coupled to the second subset. A difference circuit has an input coupled to a first node of a pixel in the first subset, and a further input coupled to a first node of a pixel in the second subset. The difference circuit generates a sensed pixel signal difference. The second common voltage generation uses the sensed difference to compensate for pixel leakage differences between the pixels of the first and second subsets. Other embodiments are also described and claimed. | 12-05-2013 |
20130328576 | MEASUREMENT OF TRANSISTOR GATE SOURCE CAPACITANCE ON A DISPLAY SYSTEM SUBSTRATE USING A REPLICA TRANSISTOR - Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A gate source capacitance of a constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be measured using a replica component that emulates the behavior of the component. | 12-12-2013 |
20130328749 | VOLTAGE THRESHOLD DETERMINATION FOR A PIXEL TRANSISTOR - A display is disclosed that includes a transparent substrate and a plurality of pixel transistors that are formed on the transparent substrate to generate an image for display. A transistor drive circuit is used to drive the pixel transistors to generate the image. The transistor drive circuit may include a gate driver. Further, a test circuit may be used to: adjust voltages that are applied by the gate driver to a pixel transistor; and determine the voltage of the gate driver when a current spike has occurred to the pixel transistor which causes the pixel transistor to turn on. Once this threshold voltage for the gate driver to turn on the pixel transistor has been determined, it may be stored in a storage device for future use by the gate driver. Other embodiments are also described and claimed. | 12-12-2013 |
20130328839 | GATE DRIVER FALL TIME COMPENSATION - A display system includes a display panel of pixels, a gate driver and a compensation unit. The gate driver receives a control signal and based on the control signal, generates a gate signal to drive a transistor included in a pixel. The compensation unit measures and compensates for a fall time of the gate driver. The compensation unit includes a replica gate driver, a peak RMS detector, a comparator and a counter. The replica gate driver generates a replica gate signal based on the control signal. The peak RMS detector calculates a peak RMS of the replica gate signal. The comparator compares the peak RMS of the replica gate signal and a reference voltage and generates a comparator value. The counter is controlled by the comparator value to generate a compensation value used to adjust the gate driver and the replica gate driver. Other embodiments are also described and claimed. | 12-12-2013 |
20130328844 | Using Clock Detect Circuitry to Reduce Panel Turn-on Time - Systems, devices, and methods for using clock detector circuitry to reduce turn-on time of an electronic display, improve image quality, and reduce operations of a host are provided. In one example, a system may include a host configured to transmit a number of signals and a display driver coupled to the host. The number of signals may include a clock signal and data signals. The display driver is configured to drive a display based at least in part on the data signals. The display driver is also configured to be reset upon detection of the clock signal without waiting for a host-issued reset signal. A clock detect circuit configured to detect the clock signal may be configured to transmit an internal reset signal to reset the display driver without a dedicated host-issued reset signal. | 12-12-2013 |
20130328846 | CHARACTERIZATION OF TRANSISTORS ON A DISPLAY SYSTEM SUBSTRATE USING A REPLICA TRANSISTOR - Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be characterized using a replica component that emulates the behavior of the component. | 12-12-2013 |
20130328851 | GROUND NOISE PROPAGATION REDUCTION FOR AN ELECTRONIC DEVICE - A system and device for reducing ground bounce in circuitry. Utilization of a common ground supplied to multiple integrated circuits reduces the complexity and costs of producing circuitry but tends to interfere with signal quality within the circuitry by subjecting each integrated circuit to the ground bounce of every other integrated circuit. By introducing a source follower to selectively decouple and/or couple slave circuits within the circuitry, the ground bounce for the overall system can be reduced, thereby increasing the efficiency of interpreting signals within the circuitry. | 12-12-2013 |
20130328852 | MEASUREMENT OF TRANSISTOR THRESHOLD VOLTAGE ON A DISPLAY SYSTEM SUBSTRATE USING A REPLICA TRANSISTOR - Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A threshold voltage of a constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be measured using a replica component that emulates the behavior of the component. | 12-12-2013 |
20130342431 | Systems and Methods for Calibrating a Display to Reduce or Eliminate Mura Artifacts - Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays. For example, pixels may be programmed to a uniform gray level before all or a substantial number of gates of the pixels are activated. The voltages on some or all source lines that supply the pixels may be measured. A mura artifact may be seen when voltage differences on the source lines are present. As such, operational parameters of the electronic display may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences. | 12-26-2013 |
20140009176 | CAPACITANCE MEASUREMENT CIRCUIT - A resistor having a known resistance is coupled in series with a device under test (DUT) having an unknown capacitance. An ac signal source having a known fundamental frequency is coupled to drive the resistor to thereby produce a first ac signal. A phase controllable signal generator produces a second ac signal. The first and second ac signals are fed to a mixer. An output of the mixer is low pass filtered. A peak detector monitors the low pass filtered output while sweeping the phase controllable signal generator, until a peak is detected. The set phase corresponding to the detected peak is then used to obtain an estimate of the unknown DUT capacitance. Other embodiments are also described and claimed. | 01-09-2014 |
20140062845 | SYSTEMS AND METHODS FOR MEASURING SHEET RESISTANCE - The present disclosure is directed to systems and methods for determining sheet resistance values in a liquid crystal display (LCD) panel. In certain embodiments, a system for determining sheet resistance values in an LCD panel may include a display driver integrated circuit (IC). The display driver IC may include a first switch coupled to a first input/output (I/O) pad and a second I/O pad such that the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source. The display driver IC may also include a second switch coupled to a third I/O pad and the second I/O pa such that the second switch has substantially the same geometry as the first switch and the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel. | 03-06-2014 |
20140097879 | PLL DUAL EDGE LOCK DETECTOR - A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. | 04-10-2014 |
20140125645 | TESTING OF INTEGRATED CIRCUIT TO SUBSTRATE JOINTS - A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed. | 05-08-2014 |
Patent application number | Description | Published |
20120330881 | Evaluation of Next Actions by Customers - System, including method, apparatus, and computer-readable storage media, for evaluating probabilities of next actions by customers to permit selective customer targeting. Customer data ( | 12-27-2012 |
20130124258 | Methods and Systems for Identifying Customer Status for Developing Customer Retention and Loyality Strategies - Embodiments of the present invention are directed to methods and systems for developing customer retention and loyalty strategies. In one aspect, a method comprises calculating ( | 05-16-2013 |
20130226691 | MULTI-CHANNEL CAMPAIGN PLANNING - A computer system for multi-channel campaign planning includes a digital processor, and computer readable instructions to plan and manage a multi-channel campaign. The instructions are embedded on a non-transitory, tangible memory device and executable by the processor. The instructions include a scenario outcome predicting module to predict an outcome for a scenario having a set of parameters defined for each channel of a phase of a plurality of iterative phases of the multi-channel campaign. The instructions include an adaptive learning module to generate an optimized learning component of the multi-channel campaign. The instructions include a decision optimization module to optimize the multi-channel campaign over the plurality of iterative phases. The instructions include a campaign execution module to execute the multi-channel campaign and collect outcome data. An initial phase of the plurality of phases is executed without prior outcome data for the scenario of the initial phase. | 08-29-2013 |
20130290097 | AWARDING A GROUP- TARGETED PROMOTION - Systems, methods, and computer-readable and executable instructions are provided for awarding a group-targeted promotion. Awarding a group-targeted promotion can include defining a first condition for a customer to join a list of promotion-eligible customers and defining a second condition for a number of groups of customers from the list to qualify for a group-targeted promotion. Awarding a group-targeted promotion can include awarding the group-targeted promotion to a group among the number of groups that complies with the second condition, wherein the method is performed by a computing device. | 10-31-2013 |
20130290109 | Eliciting A Customer's Product Preference Propensities Among Sub-Groups In A Social Network - A method to elicit a customer's product preference propensities among sub-groups, with each of the sub-groups having multiple members based on at least one common attribute, begins when customer action data is collected through the actions of the customer in the sub-group. The actions include the customer's propensities to purchase a product while within the sub-group and the customers' responses to displayed marketing messages or surveys while within the sub-group. The customer action data collected in the sub-group is analyzed to determine a customer's product preference propensities in the sub-group. The customer is targeted, when within the sub-group, with an electronic display that includes at least one product that corresponds to the customer's product preference propensities within the sub-group. | 10-31-2013 |
20140122370 | SYSTEMS AND METHODS FOR MODEL SELECTION - A non-transitory, computer-readable storage medium contains software that, when executed by a processor, causes the processor to perform various operations such as to receive transactional data, industry-specific data, output requirements, and instructions to run specific data analysis models and tests. The software may also cause the processor to identify, based on the industry-specific data and the output requirements, a set of candidate models and to assess the performance of each candidate model based on the transactional data to select a final model and to perform the selected final model on the transactional data to generate processed data. | 05-01-2014 |
20140214480 | DETERMINING A CUSTOMER PROFILE STATE - First data is received from a device, where the first data includes a usage pattern of the device by a customer. Second data of the customer is received from a social media source, the second data including information regarding sentiment about an attribute expressed by the customer. A profile state of the customer is determined based on the first data and the second data. | 07-31-2014 |