Patent application number | Description | Published |
20090315161 | DIE ATTACH METHOD AND LEADFRAME STRUCTURE - In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure). The width of at least some of these tailed lead traces in a region that overlies their associated contact post is narrower than their associated contact post. Thus, these narrowed lead traces have extensions that extend beyond their associated contact posts. The extensions provide additional surface area that gives an adhesive applied to the narrowed lead trace (as for example by stamping) room to bleed (flow) along the top surface of the lead trace on both sides of the associated contact pad. | 12-24-2009 |
20100025818 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad. | 02-04-2010 |
20100046188 | THIN FOIL SEMICONDUCTOR PACKAGE - The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages. | 02-25-2010 |
20100084748 | THIN FOIL FOR USE IN PACKAGING INTEGRATED CIRCUITS - Methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits are described. Portions of a metallic foil are ultrasonically welded to a carrier to form a foil carrier structure. The ultrasonic welding helps define a panel in the metallic foil that is suitable for packaging integrated circuits. Warpage of the thin foil can be limited in various ways. By way of example, an intermittent welding pattern that extends along the edges of the panel may be formed. Slots may be cut to define sections in the foil carrier structure. Materials for the metallic foil and the carrier may be selected to have similar coefficients of thermal expansion. An appropriate thickness for the metallic foil and the carrier may be selected, such that the warpage of the welded foil carrier structure is limited when the foil carrier structure is subjected to large increases in temperature. Foil carrier structures for use in the above methods are also described. | 04-08-2010 |
20110073481 | FOIL PLATING FOR SEMICONDUCTOR PACKAGING - Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution. | 03-31-2011 |
20110089546 | MULTIPLE LEADFRAME PACKAGE - Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 04-21-2011 |
20110269269 | LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS - The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts. Some embodiments contemplate encapsulating the dice, bonding wires, and portions of the plated foil with a plastic molding material. Portions of the metallic foil may then be removed by etching, laser ablation, or grinding. The resulting structure may then be singulated to form individual integrated circuit packages. | 11-03-2011 |
20120119343 | STACKED LEADFRAME IMPLEMENTATION FOR DC/DC CONVERTOR POWER MODULE INCORPORATING A STACKED CONTROLLER AND STACKED LEADFRAME CONSTRUCTION METHODOLOGY - Methods and systems are described for enabling the efficient fabrication of small form factor power converter packages and other devices using stacked leadframes. | 05-17-2012 |
20120326287 | DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTROLLER AND CONSTRUCTION METHODOLOGY - Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices. | 12-27-2012 |
20130019469 | Thin Foil Semiconductor Package - The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages. | 01-24-2013 |