Patent application number | Description | Published |
20100320545 | PLANAR AND NON-PLANAR CMOS DEVICES WITH MULTIPLE TUNED THRESHOLD VOLTAGES - A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material. | 12-23-2010 |
20110081754 | METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING - Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials. | 04-07-2011 |
20110081765 | METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION - A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO | 04-07-2011 |
20110108921 | SINGLE METAL GATE CMOS INTEGRATION BY INTERMIXING POLARITY SPECIFIC CAPPING LAYERS - A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer. | 05-12-2011 |
20110115026 | CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer. | 05-19-2011 |
20110115027 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 05-19-2011 |
20110212548 | METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS - A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed. | 09-01-2011 |
20110260257 | High Performance Non-Planar Semiconductor Devices with Metal Filled Inter-Fin Gaps - A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels. | 10-27-2011 |
20110303981 | Scheme to Enable Robust Integration of Band Edge Devices and Alternatives Channels - A method of forming a semiconductor device includes forming a buried oxide (BOX) layer on a semiconductor substrate, forming a silicon-on-insulator (SOI) layer on the BOX layer, depositing a hard mask including one of silicon, a nitride, and a metal oxide on the SOI layer, removing the hard mask from a first region of the semiconductor device, performing a cleaning process on the semiconductor device, wherein the hard mask is not removed from a second region of the semiconductor device by the cleaning process, epitaxially growing a semiconductor material in the first region of the semiconductor device, and removing the hard mask from the second region of the semiconductor device. | 12-15-2011 |
20120178236 | METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION - A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO | 07-12-2012 |
20120276720 | CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer. | 11-01-2012 |
20120292706 | SCHEME TO ENABLE ROBUST INTEGRATION OF BAND EDGE DEVICES AND ALTERNATIVE CHANNELS - A method of forming a semiconductor device includes forming a buried oxide (BOX) layer on a semiconductor substrate, forming a silicon-on-insulator (SOI) layer on the BOX layer, depositing a hard mask including one of silicon, a nitride, and a metal oxide on the SOI layer, removing the hard mask from a first region of the semiconductor device, performing a cleaning process on the semiconductor device, wherein the hard mask is not removed from a second region of the semiconductor device by the cleaning process, epitaxially growing a semiconductor material in the first region of the semiconductor device, and removing the hard mask from the second region of the semiconductor device. | 11-22-2012 |
20130005156 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 01-03-2013 |
20140061815 | HIGH PERFORMANCE NON-PLANAR SEMICONDUCTOR DEVICES WITH METAL FILLED INTER-FIN GAPS - A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels. | 03-06-2014 |
20150279746 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-01-2015 |
20150279937 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-01-2015 |
20150311127 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-29-2015 |
20150311303 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 10-29-2015 |
Patent application number | Description | Published |
20100308412 | CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices. | 12-09-2010 |
20110248326 | STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET - A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap. | 10-13-2011 |
20110303983 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 12-15-2011 |
20120018730 | STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES - Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. | 01-26-2012 |
20120018813 | BARRIER COAT FOR ELIMINATION OF RESIST RESIDUES ON HIGH k/METAL GATE STACKS - A technique for substantially eliminating resist residues from a gate stack that includes, from bottom to top, a high k gate dielectric and a metal gate, e.g., a high k/metal gate stack, is provided. In particular and in one embodiment, a method is disclosed in which a patterned resist and optionally a patterned barrier coating are formed atop a surface of the metal gate electrode of a high k/metal gate stack prior to patterning the metal gate electrode. At least the metal gate electrode not protected by the patterned material is then etched. The presence of the barrier coating eliminates resist residues from the resultant gate stack. The technique provided can be used in fabricating planar semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETS) including complementary metal oxide semiconductor (CMOS) field effect transistors, as well as non-planar semiconductor devices such as, for example, finFETs. | 01-26-2012 |
20120037999 | DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS - A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices. | 02-16-2012 |
20120040522 | METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS - A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology. | 02-16-2012 |
20120074533 | Structures And Techniques For Atomic Layer Deposition - In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C. | 03-29-2012 |
20120187523 | METHOD AND STRUCTURE FOR SHALLOW TRENCH ISOLATION TO MITIGATE ACTIVE SHORTS - A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide. | 07-26-2012 |
20120190179 | METHODS OF MANUFACTURING FINFET DEVICES - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 07-26-2012 |
20120193713 | FinFET device having reduce capacitance, access resistance, and contact resistance - A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers. | 08-02-2012 |
20120205727 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER - A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device. | 08-16-2012 |
20120286338 | CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices. | 11-15-2012 |
20120326217 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER - A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device. | 12-27-2012 |
20130005129 | STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET - Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap. | 01-03-2013 |
20130009249 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 01-10-2013 |
20130015509 | LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOIAANM Haran; Balasubramanian S.AACI WatervlietAAST NYAACO USAAGP Haran; Balasubramanian S. Watervliet NY USAANM Jagannathan; HemanthAACI GuilderlandAAST NYAACO USAAGP Jagannathan; Hemanth Guilderland NY USAANM Kanakasabapathy; Sivananda K.AACI NiskayunaAAST NYAACO USAAGP Kanakasabapathy; Sivananda K. Niskayuna NY USAANM Mehta; SanjayAACI NiskayunaAAST NYAACO USAAGP Mehta; Sanjay Niskayuna NY US - A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions. | 01-17-2013 |
20130015512 | LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI - A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions. | 01-17-2013 |
20130187234 | STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES - Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. | 07-25-2013 |
20130214358 | LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS - A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device. | 08-22-2013 |
20130214364 | REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER - A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate. | 08-22-2013 |
20130217190 | LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS - A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device. | 08-22-2013 |
20130217220 | REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER - A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate. | 08-22-2013 |
20130221413 | DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE - After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers. | 08-29-2013 |
20130221441 | REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV. | 08-29-2013 |
20130224939 | REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV. | 08-29-2013 |
20130256802 | Replacement Gate With Reduced Gate Leakage Current - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 10-03-2013 |
20130260549 | REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 10-03-2013 |
20130277743 | STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION - A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness. | 10-24-2013 |
20130280902 | STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION - A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness. | 10-24-2013 |
20130292746 | DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE - After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers. | 11-07-2013 |
20130307033 | Borderless Contact For An Aluminum-Containing Gate - An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. | 11-21-2013 |
20130307079 | ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION - Semiconductor devices and methods of their fabrication are disclosed. One device includes a plurality of gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the gates. The device further includes an etch resistant nitride layer that is configured to maintain the aspect ratio of the dielectric gap filling material during fabrication of the device and is disposed above the dielectric gap filling material and between the plurality of gates. | 11-21-2013 |
20130309852 | BORDERLESS CONTACT FOR AN ALUMINUM-CONTAINING GATE - An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. | 11-21-2013 |
20130309856 | ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION - Semiconductor devices and methods of their fabrication are disclosed. One method includes forming a semiconductor device structure including a plurality of dummy gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the dummy gates. An etch resistant nitride layer is applied above the dielectric gap filling material to maintain the aspect ratio of the gap filling material. In addition, the dummy gates are removed by implementing an etching process. Further, replacement gates are formed in regions of the device structure previously occupied by the dummy gates. | 11-21-2013 |
20140035038 | Structure And Method To Realize Conformal Doping In Deep Trench Applications - The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping. | 02-06-2014 |
20140038382 | Structure And Method To Realize Conformal Doping In Deep Trench Applications - The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping. | 02-06-2014 |
20140054717 | INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE - A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated. | 02-27-2014 |
20140091281 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 04-03-2014 |
20140110784 | REPLACEMENT METAL GATE FINFET - A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin. | 04-24-2014 |
20140110785 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 04-24-2014 |
20140117466 | REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV. | 05-01-2014 |
20140124873 | ROBUST REPLACEMENT GATE INTEGRATION - A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening. | 05-08-2014 |
20140291749 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 10-02-2014 |
20140291750 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 10-02-2014 |
20140327076 | ROBUST REPLACEMENT GATE INTEGRATION - A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening. | 11-06-2014 |
20150132896 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 05-14-2015 |
20150137243 | REPLACEMENT METAL GATE FINFET - A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin. | 05-21-2015 |
20150137244 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 05-21-2015 |
20150137245 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 05-21-2015 |
20150333065 | INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE - A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated. | 11-19-2015 |
20160027664 | METHOD OF PATTERNING DOPANT FILMS IN HIGH-K DIELECTRICS IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tiny (inverse of gate capacitance) mismatch. | 01-28-2016 |
20160093618 | SINGLE SOURCE/DRAIN EPITAXY FOR CO-INTEGRATING NFET SEMICONDUCTOR FINS AND PFET SEMICONDUCTOR FINS - A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein. | 03-31-2016 |
Patent application number | Description | Published |
20110133093 | DIGITAL RADIOGRAPHIC DETECTOR WITH BONDED PHOSPHOR LAYER - A digital radiographic detector having a radiation sensing element with a particulate material dispersed within a binder composition, wherein the binder composition includes a pressure-sensitive adhesive, wherein the particulate material, upon receiving radiation of a first energy level, is excitable to emit radiation of a second energy level, either spontaneously or in response to a stimulating energy of a third energy level. There is an array of photosensors, each photosensor in the array energizable to provide an output signal indicative of the level of emitted radiation of the second energy level that is received. The radiation sensing element bonds directly to, and in optical contact with, either the array of photosensors or an array of optical fibers that guide light to the array of photosensors. | 06-09-2011 |
20130001423 | RADIATION SENSING THERMOPLASTIC COMPOSITE PANELS - A transparent scintillator panel including an extruded scintillation layer comprising a thermoplastic polyolefin and a scintillator material, wherein the transparent scintillator panel has an intrinsic MTF at least 5% greater than the iH50 of a solvent-coated DRZ+ screen. Also disclosed is a scintillation detection system including a transparent scintillator panel comprising an extruded scintillation layer comprising a thermoplastic olefin and a scintillator material; and at least one photodetector coupled to the transparent scintillator panel, wherein at least one photodetector is configured to detect photons generated from the transparent scintillator panel. Further disclosed is a method of making a transparent scintillator panel including providing thermoplastic particles comprising at least one thermoplastic polyolefin and a scintillator material; and melt extruding the thermoplastic particles to form an extruded scintillation layer. | 01-03-2013 |
20130001437 | STORAGE PHOSPHOR PANEL WITH OVERCOAT COMPRISING DYE - A storage phosphor screen including a substrate; a phosphor layer disposed over the substrate; and an overcoat layer disposed over the phosphor layer, wherein the overcoat layer comprises at least one organic solvent-soluble polymer and at least one light absorbing colorant, and wherein the light absorbing colorant is dispersed within the organic solvent-soluble polymer. Also disclosed is a method of preparing a storage phosphor screen including providing a substrate; providing a phosphor solution comprising a solvent, at least one stimulable phosphor, and a binder; providing an overcoat solution comprising a solvent, at least one organic solvent-soluble polymer and at least one light absorbing colorant; forming a phosphor layer over a surface of the substrate with the phosphor solution; and forming an overcoat layer over the phosphor layer with the overcoat solution, wherein the light absorbing colorant is dispersed within the overcoat layer. | 01-03-2013 |
20130026392 | PATTERNED RADIATION-SENSING THERMOPLASTIC COMPOSITE PANELS - A patterned scintillator panel including an extruded scintillator layer comprising a thermoplastic polyolefin and a scintillator material, wherein the scintillator layer comprises a pattern. Also disclosed is a method of making a patterned scintillator panel including forming a scintillator layer by melt extrusion, the scintillator layer comprising thermoplastic particles comprising a thermoplastic polyolefin and a scintillator material; and patterning the scintillator layer. Further disclosed is a method of making a patterned scintillator panel including forming a scintillator layer by injection molding, the scintillator layer comprising thermoplastic particles comprising a thermoplastic polyolefin and a scintillator material; and patterning the scintillator layer | 01-31-2013 |
20130126753 | X-RAY IMAGING PANEL WITH THERMALLY-SENSITIVE ADHESIVE AND METHODS OF MAKING THEREOF - Provided herein are scintillator screens comprising a substrate; a scintillation layer disposed over the substrate, the scintillation layer comprising a scintillator material; and an adhesive layer disposed by solvent coating over the scintillation layer, the adhesive layer comprising solvent-coatable thermally-sensitive elastomer, wherein the adhesive layer has a dust adhesion of ≦1 dust particles/sq.in. | 05-23-2013 |
20130177773 | X-RAY IMAGING PANEL WITH THERMALLY-SENSITIVE ADHESIVE AND METHODS OF MAKING THEREOF - Provided herein are laminated devices including an extruded scintillation screen comprising a scintillator material that does not attract dust, and a thermally-sensitive elastomer binder; and a fiber optic plate. Also provided herein are methods of making a laminated device and methods of making an X-ray imaging panel. | 07-11-2013 |
20130220514 | METHOD OF MANUFACTURING DIGITAL DETECTORS - There is described a method of manufacturing a digital radiography panel. The method includes providing a scintillator screen and spray coating an acrylic adhesive composition on the scintillator screen. A flat panel detector and the scintillator screen with acrylic adhesive composition are compressed together at a force of about 5 psi to about 15 psi, at an atmospheric pressure of about 0.3 Torr to about 100.0 Torr for a time sufficient to affix the flat panel detector to the scintillator screen to form the digital radiography panel. | 08-29-2013 |
20130221225 | COATINGS FOR DIGITAL DETECTORS - Described is a scintillator screen that includes a supporting layer having a phosphor dispersed in a polymeric binder disposed on the supporting layer and a barrier layer disposed on the polymeric binder. The barrier layer includes a non-moisture absorbing polymer selected from the group consisting of polyethylene terephthalate, cellulose diacetate, ethylene vinyl acetate and polyvinyl butyraldehyde. The barrier layer has a thickness of less than 1 micron. An antistatic layer is disposed on the barrier layer. The antistatic layer includes poly(3,4-ethylenedixythiophene)-poly(styrene sulfonate) (PEDOT/PSS) dispersed in a polymer selected from the group consisting of a polyester and a polyurethane. The antistatic layer has a transparency of greater than 95 percent at a wavelength of from about 400 nm to 600 nm. | 08-29-2013 |
20130221229 | ADHESIVE LAYER FOR DIGITAL DETECTORS - There is described a digital radiography panel that includes a scintillator screen, an adhesive layer and a flat panel detector. The scintillator screen includes a supporting layer; a phosphor dispersed in a polymeric binder disposed on the supporting layer and an antistatic layer disposed on the polymeric binder, wherein the antistatic layer has a transparency of greater than 95 percent at a wavelength of from about 400 nm to 600 nm and a surface resistivity of less than 10 | 08-29-2013 |
20140113130 | LAMINATED STORAGE PHOSPHOR PANEL WITH THERMALLY-SENSITIVE ADHESIVE AND METHODS OF MAKING THEREOF - Provided herein are exemplary embodiments for phosphor screen including a substrate, a stimulable phosphor layer disposed over the substrate, the stimulable phosphor layer including a stimulable phosphor material, and an adhesive layer disposed by solvent coating over the stimulable phosphor layer, the adhesive layer including solvent-coatable thermally-sensitive elastomers, where the adhesive layer has a dust adhesion of ≦1 dust particles/sq.in. | 04-24-2014 |
20140186594 | PATTERNED RADIATION-SENSING THERMOPLASTIC COMPOSITE PANELS - A patterned scintillator panel including an extruded scintillator layer comprising a thermoplastic polyolefin and a scintillator material, wherein the scintillator layer comprises a pattern. Also disclosed is a method of making a patterned scintillator panel including forming a scintillator layer by melt extrusion, the scintillator layer comprising thermoplastic particles comprising a thermoplastic polyolefin and a scintillator material; and patterning the scintillator layer. Further disclosed is a method of making a patterned scintillator panel including forming a scintillator layer by injection molding, the scintillator layer comprising thermoplastic particles comprising a thermoplastic polyolefin and a scintillator material; and patterning the scintillator layer. | 07-03-2014 |
20140291528 | RADIATION SENSING THERMOPLASTIC COMPOSITE PANELS - A storage phosphor panel can include an extruded inorganic storage phosphor layer including a thermoplastic polyolefin and an inorganic storage phosphor material, where the extruded inorganic storage phosphor panel has a DQE comparable to that of a traditional extruded inorganic solvent coated inorganic storage phosphor screen. Also disclosed is an inorganic storage phosphor detection system including an extruded inorganic storage phosphor panel that can include an extruded inorganic storage phosphor layer including a thermoplastic olefin and an inorganic storage phosphor material; and photodetector(s) coupled to the extruded inorganic storage phosphor panel to detect photons generated from the extruded inorganic storage phosphor panel. Further disclosed is a method of making an extruded inorganic storage phosphor panel that can include providing thermoplastic particles including at least one thermoplastic polyolefin and an inorganic storage phosphor material; and melt extruding the thermoplastic particles to form an extruded inorganic storage phosphor layer. | 10-02-2014 |
20150301198 | DIGITAL RADIOGRAPHY DETECTOR - Described is a scintillator screen including a plurality of filaments. Each of the plurality of filaments includes scintillating particles dispersed within a thermoplastic polymer. The thermoplastic polymer includes an elastic additive. The scintillating particles are from about 10 volume percent to about 60 volume percent of each of the plurality of filaments. Each of the plurality of filaments has a refractive index of greater than or equal to 1.5. The plurality of filaments are substantially parallel to each other and are at a volume packing of from about 60 percent to about 90 percent. | 10-22-2015 |
Patent application number | Description | Published |
20080298444 | Dsl System - Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface. | 12-04-2008 |
20090323903 | METHOD AND APPARATUS FOR ANALYZING AND MITIGATING NOISE IN A DIGITAL SUBSCRIBER LINE - Data indicative of a level of stability of a DSL link is received. Based on the received data, it is determined whether the data indicates a level of stability of the DSL link that is above or below a minimum threshold. If the level of stability of the DSL link is below the minimum threshold, die noise associated with the DSL link before the time of failure is compared with the noise associated with the DSL link after the time of failure. If the difference between the noise before and after the time of failure exceeds a threshold, then the difference in noise is characterized as a stationary noise associated with the DSL link. However, if the difference between the noise before and after the time of failure is below the threshold, a determination is made whether the failure is associated with a loss of power to the DSL link or a severe impulse noise event—the difference in noise is characterized accordingly. Finally, the characterization of the noise associated with the DSL link is preserved for subsequent possible reconfiguration of the DSL link to improve link stability. | 12-31-2009 |
20100074312 | HIGH SPEED MULTIPLE USER MULTIPLE LOOP DSL SYSTEM - A high speed multiple user multiple-loop DSL system is described. In one embodiment, it includes a first DSL loop to carry DSL traffic to a first user and a second DSL loop to carry DSL traffic to a second user. A first junction connects the traffic of the first DSL loop to a third DSL loop, and a second junction connects the traffic of the second DSL loop to the third DSL loop. | 03-25-2010 |
20100135482 | INTERFERENCE CANCELLATION SYSTEM - An adaptive interference cancellation system is described. In one example the system operates by receiving a data signal using a DSL (Digital Subscriber Line) and receiving a reference signal, the reference signal corresponding, in part, to noise on the data signal. The reference signal is classified and a noise cancellation signal is applied to the data signal based on the classification. | 06-03-2010 |
20110299579 | DSL SYSTEM - Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface. | 12-08-2011 |
20130230084 | METHOD AND APPARATUS FOR ANALYZING AND MITIGATING NOISE IN A DIGITAL SUBSCRIBER LINE - Data indicative of a level of stability of a DSL link is received. Based on the received data, it is determined whether the data indicates a level of stability of the DSL link that is above or below a minimum threshold. If the level of stability of the DSL link is below the minimum threshold, die noise associated with the DSL link before the time of failure is compared with the noise associated with the DSL link after the time of failure. If the difference between the noise before and after the time of failure exceeds a threshold, then the difference in noise is characterized as a stationary noise associated with the DSL link. However, if the difference between the noise before and after the time of failure is below the threshold, a determination is made whether the failure is associated with a loss of power to the DSL link or a severe impulse noise event—the difference in noise is characterized accordingly. Finally, the characterization of the noise associated with the DSL link is preserved for subsequent possible reconfiguration of the DSL link to improve link stability. | 09-05-2013 |
20140133539 | METHOD AND APPARATUS FOR ANALYZING AND MITIGATING NOISE IN A DIGITAL SUBSCRIBER LINE - Data indicative of a level of stability of a DSL link is received. Based on the received data, it is determined whether the data indicates a level of stability of the DSL link that is above or below and minimum threshold. If the level of stability of the DSL link is below the minimum threshold, die noise associated with the DSL link before the time of failure is compared with the noise of failure. If the difference between the noise before and after the time of failure exceeds a threshold, then the difference in noise is characterized as a stationary noise associated with the DSL link. However, if the difference between the noise before and after the time of failure is below the threshold, a determination is made whether the failure is associated with a loss of power to the DSL link or a severe impulse noise event the difference in noise is characterized accordingly. Finally, the characterization of the noise associated with the DSL link is preserved for subsequent possible reconfiguration of the DSL link to improve link stability. | 05-15-2014 |
20150222486 | DSL SYSTEM - Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface. | 08-06-2015 |
Patent application number | Description | Published |
20090192822 | METHODS AND COMPUTER PROGRAM PRODUCTS FOR NATURAL LANGUAGE PROCESSING FRAMEWORK TO ASSIST IN THE EVALUATION OF MEDICAL CARE - A computerized method for evaluating medical reports includes identifying at least one or more medical reports stored in a database related to the medical condition, validating the identified medical reports by determining if key words associated with the medical condition found in the at least one or more reports are surrounded by a negative context and extracting relevant data from the medical reports. The exemplary method also includes evaluating the relevant data from the medical reports with provisions set forth in clinical guidelines corresponding to a medical condition, storing a flag identifying one or more of the medical reports as noncompliant when its corresponding relevant data does not comply with the provisions set forth in the clinical guideline unless a valid contraindication applies and displaying the medical reports identified as noncompliant. | 07-30-2009 |
20100250236 | COMPUTER-ASSISTED ABSTRACTION OF DATA AND DOCUMENT CODING - A computer-assisted method of abstracting and coding data includes receiving one or more documents is disclosed. The methods and systems extract information from a record based on extraction rules that correspond to an identified record type, determine codes corresponding to the information extracted from the record, present the correspondence between the extracted information and the codes, receive from the user-input device a validation of the correspondence between the extracted information and one of the codes, and output a report including the validated information and the validated code. | 09-30-2010 |
20120215782 | Computer-Assisted Abstraction for Reporting of Quality Measures - Methods and systems are disclosed for tracking quality measures in abstracted documents. Embodiments include, determining, based on the abstracted content, a quality measure category, obtaining a quality measure definition corresponding to a quality measure included in the determined quality measure category, determining, based on keywords corresponding to the criterion, whether a portion of the abstracted content satisfies a criterion, recording, in association with the criterion, a reference to the portion of the abstracted content that satisfies the criterion; and selectively generating, a report including the query corresponding to the criterion, a query response, and the portion of the abstracted content satisfying the criterion. | 08-23-2012 |
20140006431 | Automated Clinical Evidence Sheet Workflow | 01-02-2014 |
20140278549 | Collaborative Synthesis-Based Clinical Documentation - A graphical user interface, referred to herein as a virtual whiteboard, that provides both: (1) an automatically prioritized display of information related to a particular patient that is tailored to the current user of the system, and (2) a “scratch pad” area in which multiple users of the system may input free-form text and other data for sharing with other users of the system. When each user of the system accesses the virtual whiteboard, the system: (1) automatically prioritizes the patient information based on characteristics of the user and displays the automatically prioritized patient information to that user, and (2) displays the contents of the scratch pad to the user. As a result, the whiteboard displays both information that is tailored to the current user and information that is common to all users (i.e., not tailored to any particular user). | 09-18-2014 |
20140278553 | Dynamic Superbill Coding Workflow - A computer system generates an initial set of billing codes based on one or more documents (e.g., clinical notes) representing a patient encounter, such as clinical notes created by a physician. The system expands the initial set of billing codes based on a billing code standard to create an expanded set of billing codes for consideration by the physician. The system provides output representing the expanded billing code set to the physician. The physician selects one or more billing codes from the expanded billing code set for inclusion in a final billing code set for use in a bill for the services provided in the patient encounter. | 09-18-2014 |
20140304002 | Collaborative Synthesis-Based Clinical Documentation - A graphical user interface, referred to herein as a virtual whiteboard, that provides both: (1) an automatically prioritized display of information related to a particular patient that is tailored to the current user of the system, and (2) a “scratch pad” area in which multiple users of the system may input free-form text and other data for sharing with other users of the system. When each user of the system accesses the virtual whiteboard, the system: (1) automatically prioritizes the patient information based on characteristics of the user and displays the automatically prioritized patient information to that user, and (2) displays the contents of the scratch pad to the user. As a result, the whiteboard displays both information that is tailored to the current user and information that is common to all users (i.e., not tailored to any particular user). | 10-09-2014 |
20140343963 | Dynamic Superbill Coding Workflow - A computer system generates an initial set of billing codes based on one or more documents (e.g., clinical notes) representing a patient encounter, such as clinical notes created by a physician. The system expands the initial set of billing codes based on a billing code standard to create an expanded set of billing codes for consideration by the physician. The system provides output representing the expanded billing code set to the physician. The physician selects one or more billing codes from the expanded billing code set for inclusion in a final billing code set for use in a bill for the services provided in the patient encounter. | 11-20-2014 |
20150081716 | Computer-Assisted Abstraction for Reporting of Quality Measures - Methods and systems are disclosed for tracking quality measures in abstracted documents. Embodiments include, determining, based on the abstracted content, a quality measure category, obtaining a quality measure definition corresponding to a quality measure included in the determined quality measure category, determining, based on keywords corresponding to the criterion, whether a portion of the abstracted content satisfies a criterion, recording, in association with the criterion, a reference to the portion of the abstracted content that satisfies the criterion; and selectively generating, a report including the query corresponding to the criterion, a query response, and the portion of the abstracted content satisfying the criterion. | 03-19-2015 |
20150088504 | Computer-Assisted Abstraction of Data and Document Coding - A computer-assisted method of abstracting and coding data includes receiving one or more documents is disclosed. The methods and systems extract information from a record based on extraction rules that correspond to an identified record type, determine codes corresponding to the information extracted from the record, present the correspondence between the extracted information and the codes, receive from the user-input device a validation of the correspondence between the extracted information and one of the codes, and output a report including the validated information and the validated code. | 03-26-2015 |