Patent application number | Description | Published |
20090031192 | CHANNEL ENCODING APPARATUS AND METHOD - A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream. | 01-29-2009 |
20090106637 | Concatenated decoder and concatenated decoding method - A concatenated decoder and concatenated decoding method are provided. The concatenated decoder, including: an inner decoder to receive an input bit stream, inner-decode the received input bit stream, and generate a first bit stream; and an outer decoder to generate error information about the received first bit stream, according to the generated error information, transmit an iterative decoding continuation request to the inner decoder or outer-decode the first bit stream to generate a second bit stream. | 04-23-2009 |
20090182934 | Memory device and method of multi-bit programming - Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated. | 07-16-2009 |
20090223759 | Shock absorber for drawer - Disclosed is a shock absorber for a drawer. The shock absorber includes a body filled with fluid, a piston member inserted into the body while being coupled with a rod, and a buffering member installed in the body to prevent the body from being broken by receiving pressure change of fluid when the piston member moves forward and backward. According to the shock absorber, high impact force generated when the drawer is closed can be absorbed and efficiently distributed, so that the drawer can be silently operated. | 09-10-2009 |
20090304570 | MANUFACTURING METHODS OF MESOPOROUS CARBON STRUCTURE WITH SPRAY DRYING OR SPRAY PYROLYSIS AND COMPOSITION THEREOF - Disclosed is a method for preparing a porous carbon structure, the method comprising the steps of: (a) mixing a carbon precursor, a pyrolytic template, which is pyrolyzed at the carbonization temperature of the carbon precursor or removed by post-treatment after the carbonization of the carbon precursor so as to form pores, and a solvent, to prepare a spray solution; and (b) subjecting the spray solution either to spray pyrolysis or to spray drying and then spray pyrolysis, so as to form a carbonized carbon structure, and then removing the template from the carbon structure. A mesoporous spherical carbon prepared according to the disclosed method may have a large specific surface area and a large pore volume through the control of the kind and concentration of template, and thus can be used in a wide range of applications, including catalysts, adsorbents, electrode materials, materials for separation and purification, and materials for storing hydrogen and drugs. | 12-10-2009 |
20100077279 | Non-Volatile Memory Devices, Systems, and Data Processing Methods Thereof - Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein. | 03-25-2010 |
20100103731 | METHOD ANALYZING THRESHOLD VOLTAGE DISTRIBUTION IN NONVOLATILE MEMORY - A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by reading data stored in the memory cells and determining read index data from the read data, and estimating a distribution characteristic for at least one of the overlapping threshold voltage distributions using the read index data. | 04-29-2010 |
20100115225 | Memory Device and Memory System Including the Same - Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed. | 05-06-2010 |
20100115377 | METHOD OF ESTIMATING AND CORRECTING ERRORS IN MEMORY CELLS - A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups. | 05-06-2010 |
20100118608 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME - A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit. | 05-13-2010 |
20100170062 | Door Damper - Disclosed is a door damper, in which a safety check valve is installed in consideration of the case in which an impact exceeding a design pressure will be applied, thereby absorbing the impact to enable a door to be closed safely and smoothly. In the door damper, a safety check valve is installed in a piston, and thus is opened in cooperation with another check valve installed between a spring holder and the piston when the pressure exceeding a design pressure is applied. Thereby, when the impact exceeding the design pressure occurs, the safety check valve can absorb the impact to prevent damage. A channel can be adjusted by only ridges formed on an outer circumference of the check valve, so that productivity can be improved thanks to easy tolerance management. Further, an oil seal is not contracted or deformed in spite of long-term use. | 07-08-2010 |
20100195389 | FLASH MEMORY DEVICE AND METHODS PROGRAMMING/READING FLASH MEMORY DEVICE - Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states. | 08-05-2010 |
20100202198 | Semiconductor memory device and data processing method thereof - Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states. | 08-12-2010 |
20100223530 | SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - Provided are a semiconductor memory device and a data processing method thereof. The semiconductor memory device includes a nonvolatile memory and a memory controller. The nonvolatile memory stores data a plurality of memory cells. The memory controller rearranges data by various operations such as a modulation code operation and processes the data according to an ECC operation to reduce the interference between the memory cells. | 09-02-2010 |
20100235711 | Data Processing System with Concatenated Encoding and Decoding Structure - A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword. | 09-16-2010 |
20100238705 | NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME - A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the de-interleaving circuit is configured to store program data to be written interleaved into the memory cell array. The read/write circuit is configured to control the interleaved/deinterleaved data input/output between the memory cell array and the storage circuit. The write operation unit size may be the same or different from the read operation unit size. The storage circuit stores the program data of integer k times of a common divisor of a read operation unit size and a write operation unit size of the read/write circuit, wherein k may equal ‘m’ (the number of bits stored in each memory cell of the NVM). | 09-23-2010 |
20100241928 | Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection - A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data. | 09-23-2010 |
20100246286 | Nonvolatile memory device, method, system including the same, and operating method thereof - In a method of operating a nonvolatile memory device, data is read using a read level, and a range of logic values for erasure-decoding the read data is set. The bits of the read data corresponding to the set range of logic values are set as erasure bits, and an erasure decoding operation is performed. | 09-30-2010 |
20100265764 | Methods of accessing storage devices - Methods of accessing storage devices. The methods include rearranging a writing order of continuous first and second data according to a reading order, and writing the first and second data in a first and second storage region of the storage device, respectively, according to the writing order. The reading order reads the second storage region first that provides interference on the first storage region. | 10-21-2010 |
20100302850 | Storage device and method for reading the same - The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution. | 12-02-2010 |
20100306583 | Memory Systems and Defective Block Management Methods Related Thereto - Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition. | 12-02-2010 |
20100332737 | FLASH MEMORY PREPROCESSING SYSTEM AND METHOD - A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data. | 12-30-2010 |
20110032758 | NONVOLATILE MEMORY DEVICE OUTPUTTING ANALOG SIGNAL AND MEMORY SYSTEM HAVING THE SAME - A memory system and a nonvolatile memory device therein are disclosed. The memory system comprises a memory device outputting a plurality of analog signals during a read operation, a converter to convert the plurality of analog signals into binary data, and a memory controller to operate an error correction operation on the binary data. The error correction operation uses a soft decision algorithm. | 02-10-2011 |
20110125975 | INTERLEAVING APPARATUSES AND MEMORY CONTROLLERS HAVING THE SAME - An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data. | 05-26-2011 |
20110216588 | MULTI-BIT CELL MEMORY DEVICES USING ERROR CORRECTION CODING AND METHODS OF OPERATING THE SAME - A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits. | 09-08-2011 |
20110216598 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 09-08-2011 |
20110219288 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE, METHOD OF OPERATING CONTROLLER, AND METHOD OF OPERATING MEMORY SYSTEM INCLUDING THE SAME - An method of operating a memory system including a nonvolatile memory device and a controller. The method includes receiving a source word, converting the received source word to a codeword, and programming the converted codeword in the nonvolatile memory device. A length of the converted codeword can be greater than a length of the received source word, and a difference between the numbers of first and second digital bits of the converted codeword can be less than a reference value. | 09-08-2011 |
20110249496 | PROGRAM METHOD OF MULTI-BIT MEMORY DEVICE AND DATA STORAGE SYSTEM USING THE SAME - Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels. | 10-13-2011 |
20110258667 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - An electronic device and a method of controlling the electronic device are provided. The electronic device includes a broadcast receiving unit that receives a broadcast content, a communication unit that receives power information associated with a mart grid, the power information including at least one of per-time slot electricity rate information and power demand information, and a controller that selectively performs one of an operation of outputting the broadcast content received through the broadcast receiving unit and an operation of storing the received broadcast content in an internal memory or an external memory considering the received power information. | 10-20-2011 |
20110261267 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - Provided are an electronic device and a method for controlling the same. The electronic device comprises a communication unit for receiving electricity service charge information and a controller for outputting a control signal to control output property to output predetermined contents based on the received electricity service charge information. | 10-27-2011 |
20110276777 | DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device. | 11-10-2011 |
20110283166 | STORAGE DEVICE HAVING A NON-VOLATILE MEMORY DEVICE AND COPY-BACK METHOD THEREOF - A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation. | 11-17-2011 |
20110291794 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - An electronic device is provided that comprises a communication unit; an output unit; and a controller configured to output at least one of a first user interface and a second user interface through the output unit, in a case of entering a high rate time slot determined based on electricity rate information received through the communication unit while outputting contents through the output unit, wherein the first user interface queries whether to continuously output the contents through the output unit and wherein the second user interface is to receive a selection associated with a replacement electronic device for outputting the contents. | 12-01-2011 |
20120001490 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - An electronic device and a method of controlling the electronic device are provided. Based on smart grid information received from a smart grid network, contents are played by an electronic device that consumes less power at a time slot during which a high electricity rate applies, thus minimizing electricity fees. | 01-05-2012 |
20120043821 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING POWER SUPPLY THEREIN - Disclosed is an electronic device, which includes an external power supply unit configured to receive power from an external power source and an auxiliary power storage unit configured to be charged upon receiving the power from the external power supply unit and store the power. The electronic device further includes a first switching element connected to the external power supply unit and the auxiliary power storage unit, the first switching element configured to select any one of the external power supply unit and the auxiliary power storage unit as a power source, a power information receiver configured to receive power information including at least one of electric rate information and power demand information, and a controller configured to control the first switching element based on the power information received from the power information receiver. | 02-23-2012 |
20120069657 | MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF - A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array. | 03-22-2012 |
20120233518 | Data Processing Systems And Methods Providing Error Correction - A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed. | 09-13-2012 |
20120272017 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM AND RANDOM DATA READ METHOD THEREOF - A random data reading method of a nonvolatile memory device includes receiving an initial seed corresponding to a selected page of the nonvolatile memory device and relative location information of read-requested random data in the selected page. The method further includes generating a seed for randomizing the random data by subjecting the initial seed and the location information to a finite field arithmetic operation, and de-randomizing the random data based on a random sequence generated from the seed. | 10-25-2012 |
20130198440 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND BLOCK MANAGING METHOD, AND PROGRAM AND ERASE METHODS THEREOF - In one embodiment, the method includes overwriting a memory cell storing m-bit data to store n-bit data, where n is less than or equal to m. The memory cell has one of a first plurality of program states when storing the m-bit data, and the memory cell has one of a second plurality of program states when storing the n-bit data. The second plurality of program states include at least one program state not in the first plurality of program states. | 08-01-2013 |
20130264880 | WIRELESS POWER SUPPLY DEVICE, ELECTRONIC DEVICE CAPABLE OF RECEIVING WIRELESS POWER, AND METHOD FOR CONTROLLING TRANSMISSION OF WIRELESS POWER - The present application relates to a wireless power supply device and wireless power transmission control in an electronic device capable of receiving wireless power. According to an embodiment of the present application, the electronic device capable of receiving wireless power comprises a communication unit which receives power information including at least one piece of electricity bill information and power demand information. Also, the electronic device comprises a wireless power receiving unit which receives wireless power wirelessly supplied from a wireless power supply device, and a power converting unit which converts the wireless power received into power that can be used in the electronic device. By using various embodiments suggested by the present application, use of power wirelessly supplied can be efficiently controlled, and accordingly, electric power can be economically and efficiently used. | 10-10-2013 |
20130307664 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - An electronic device can include: a communication unit; a display unit for display contents; and a controller configured to: display a user interface for querying whether to continuously display the contents or stop a display of the contents on the display unit, when the electronic device enters a high rate time slot determined based on electricity rate information received through the communication unit, receive an input for stopping the display of the contents through the user interface, and output a power ON signal and source information of the contents to a replacement electronic device. | 11-21-2013 |
20140056064 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 02-27-2014 |
20140185375 | MEMORY SYSTEM TO DETERMINE INFERENCE OF A MEMORY CELL BY ADJACENT MEMORY CELLS, AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 07-03-2014 |
20140372714 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM AND RANDOM DATA READ METHOD THEREOF - A random data reading method of a nonvolatile memory device includes receiving an initial seed corresponding to a selected page of the nonvolatile memory device and relative location information of read-requested random data in the selected page. The method further includes generating a seed for randomizing the random data by subjecting the initial seed and the location information to a finite field arithmetic operation, and de-randomizing the random data based on a random sequence generated from the seed. | 12-18-2014 |