Patent application number | Description | Published |
20100214858 | Delay locked loop circuit for preventing failure of coarse locking - A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance. | 08-26-2010 |
20120176170 | DELAY LOCKED LOOP CIRCUIT FOR PREVENTING FAILURE OF COARSE LOCKING - A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. Accordingly, a failure of a coarse locking may be prevented thus facilitating improved circuit performance. | 07-12-2012 |
20130069689 | Method For Operating Memory Device And Apparatuses Performing The Method - According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal. | 03-21-2013 |
20140149631 | MEMORY MODULES AND MEMORY SYSTEMS INCLUDING THE SAME - A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation. | 05-29-2014 |
20140181567 | COMMAND CONTROL CIRCUIT FOR MEMORY DEVICE AND MEMORY DEVICE INCLUDING THE SAME - Exemplary embodiments disclose a command control circuit including a command decoder configured to generate an internal command signal using a chip select (CS) signal and a command signal, and a CS gating logic configured to provide the CS signal to the command decoder, wherein the CS gating logic is further configured to provide the CS signal to the command decoder in response to a clock enable (CKE) signal being at a first level, and block the CS signal from the command decoder in response to the CKE signal being at a second level. | 06-26-2014 |
20140253188 | DIVIDED CLOCK GENERATION DEVICE AND DIVIDED CLOCK GENERATION METHOD - A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals. | 09-11-2014 |
20140254295 | MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells. | 09-11-2014 |
20140258607 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal. | 09-11-2014 |
20140266351 | DELAY-LOCKED LOOP CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay-locked loop circuit includes a phase detector and a coarse-lock detector. The phase detector receives a feedback clock and a first clock to generate first and second phase detecting signals, respectively. The coarse-lock detector generates a coarse-lock signal based on changes of phase of the first and second phase detecting signals. | 09-18-2014 |
20140270785 | ELECTRO-PHOTONIC MEMORY SYSTEM - An electro-photonic memory system includes a semiconductor memory device for storing data by receiving a first electrical signal, a memory controller for generating a second electrical signal to control the semiconductor memory device, an electrical-to-optical converter for receiving the second electrical signal from the memory controller and converting the second electrical signal into an optical signal, the electrical-to-optical converter separate from the memory controller, and an optical-to-electrical converter for receiving the optical signal from the electrical-to-optical converter and converting the optical signal into the first electrical signal. | 09-18-2014 |