Patent application number | Description | Published |
20130024737 | TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS - A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit. | 01-24-2013 |
20130036829 | OPTICAL SHEAR SENSOR AND METHOD OF PRODUCING SUCH AN OPTICAL SHEAR SENSOR - An optical shear sensor that includes a first and second outer surface at opposing sides and a sensing element is disclosed. In one aspect, the sensing element has an optoelectronic source for emitting light of a predetermined wavelength and having a source front surface where light exits the optoelectronic source, and a photodetector for detecting light of the predetermined wavelength and having a detector front surface where light of the optoelectronic source is received. The optoelectronic source is positioned along the first outer surface and emits light towards the second outer surface. A flexible sensing layer transparent to the predetermined wavelength covers the front surface of the optoelectronic source and the front surface of the photodetector. Upon application of a shear stress, the sensing layer deforms elastically and the outer surfaces are displaced along directions parallel to each other and the source front surface so the intensity of light detected by the photodetector changes. | 02-14-2013 |
20130052815 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function. | 02-28-2013 |
20130072124 | METHOD AND SYSTEM FOR ANALOG BEAMFORMING IN WIRELESS COMMUNICATION SYSTEMS - A method of analog beamforming in a wireless communication system is disclosed. The system has a plurality of transmit antennas and receive antennas. In one aspect, the method includes determining information representative of communication channels formed between a transmit antenna and a receive antenna of the plurality of antennas, defining a set of coefficients representing jointly the transmit and the receive beamforming coefficients, determining a beamforming cost function using the information and the set of coefficients, determining an optimized set of coefficients by exploiting the beamforming cost function, and separating the optimized set of coefficients into optimized transmit beamforming coefficients and optimized receive beamforming coefficients. | 03-21-2013 |
20130075876 | SEALED POROUS MATERIALS, METHODS FOR MAKING THEM, AND SEMICONDUCTOR DEVICES COMPRISING THEM - A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices. | 03-28-2013 |
20130078155 | Method and Device for Thermal Insulation of Micro-Reactors - A micro-fluidic device is described. The micro-fluidic device includes a semiconductor substrate; at least one micro-reactor in the semiconductor substrate; one or more micro-fluidic channels in the semiconductor substrate, connected to the at least one micro-reactor; a cover layer bonded to the semiconductor substrate for sealing the one or more micro-fluidic channels; and at least one through-substrate trench surrounding the at least one micro-reactor and the one or more micro-fluidic channels. | 03-28-2013 |
20130084700 | Method for Selectively Depositing Noble Metals on Metal/Metal Nitride Substrates - A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber. | 04-04-2013 |
20130100577 | Method for Forming a MIMCAP Structure and the MIMCAP Structure Thereof - A method for forming a Metal-Insulator-Metal Capacitor (MIMCAP) structure and the MIMCAP structure thereof are described. An example electronic device includes a first electrode, and a layer of a dielectric material including titanium oxide and a first dopant ion. The layer of the dielectric material is formed on the first electrode. The first dopant ion has a size mismatch of 10% or lower compared to the Ti | 04-25-2013 |
20130102121 | Oxygen Diffusion Barrier Comprising Ru - A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer. | 04-25-2013 |
20130102140 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode. | 04-25-2013 |
20130113549 | Variable Capacitor Circuit and Method - A variable capacitor circuit is disclosed. The variable capacitor circuit includes a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which the equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal. | 05-09-2013 |
20130116577 | Biomedical Acquisition System With Motion Artifact Reduction - A system for the analysis of ECG signals is disclosed. The system may comprise (i) at least one readout channel, configured to receive an analogue ECG signal acquired from at least one electrode attached to a body, and to extract an analogue measured ECG signal and analogue electrode-skin impedance signals; (ii) at least one ADC, configured to convert those extracted analogue signals at the readout channel into digital signals; (iii) a digital adaptive filter unit, configured to calculate a digital motion artifact estimate based on said digital versions of the measured ECG signal and the electrode-skin impedance signals; (iv) at least one DAC, configured to convert said digital motion artifact estimate into an analogue signal; and (v) a feedback loop for sending said analogue motion artifact estimate signal back to the readout channel configured to deduct said analogue motion artifact estimate signal from said analogue measured ECG signal. | 05-09-2013 |
20130116588 | System and Method for the Analysis of Electrocardiogram Signals - A microprocessor configured to receive and process digitized signals derived from an analogue ECG signal is provided. An example microprocessor comprises a beat detection unit configured to receive the in-phase and quadrature phase band power signals, calculate a band power value and an adaptive threshold value, and compare said band power value with said adaptive threshold value to detect a QRS complex of the ECG signal indicative of a detected valid beat; and an R peak detection unit configured to receive the digital ECG signal and information about the detected valid beat, select a portion of the received ECG signal as a first time window around the detected valid beat; determine the location of a first R peak position; and perform a time domain search in a second time window around said first R peak position in order to refine the location of an R peak position. | 05-09-2013 |
20130119014 | PROTECTIVE TREATMENT FOR POROUS MATERIALS - A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value T | 05-16-2013 |
20130130180 | Method for Producing a GaNLED Device - A method for producing a GaNLED device, wherein a stack of layers comprising at least a GaN layer is texturized, is disclosed. The method involves (i) providing a substrate comprising on its surface said stack of layers, (ii) depositing a resist layer directly on said stack, (iii) positioning a mask above said resist layer, said mask covering one or more first portions of said resist layer and not covering one or more second portions of said resist layer, (iv) exposing said second portions of said resist layer to a light source, (v) removing the mask, and (vi) bringing the resist layer in contact with a developer comprising potassium, wherein said developer removes said resist portions that have been exposed and texturizes the surface of at least the top layer of said stack by wet etching said surface, in the areas situated underneath said resist portions that have been exposed. | 05-23-2013 |
20130132529 | METHOD FOR DETERMINING A DATA FORMAT FOR PROCESSING DATA AND DEVICEEMPLOYING THE SAME - A method for determining a data format for processing data to be transmitted along a communication path is disclosed. In one aspect, the method includes identifying at run-time an operational configuration based on received information on the conditions for communication on the communication path. The method may also include selecting according to the identified operational configuration, a data format for processing data to be transmitted among a plurality of predetermined data formats. | 05-23-2013 |
20130134382 | Selector Device for Memory Applications - The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state. | 05-30-2013 |
20130134436 | METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate. | 05-30-2013 |
20130153923 | ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF - Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. | 06-20-2013 |
20130154112 | Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof - The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates. | 06-20-2013 |
20130155409 | METHOD FOR DETERMINING THE ACTIVE DOPING CONCENTRATION OF A DOPED SEMICONDUCTOR REGION - A method and system for optically determining a substantially fully activated doping profile are disclosed. The substantially fully activated doping profile is characterized by a set of physical parameters. In one aspect, the method includes obtaining a sample comprising a fully activated doping profile and a reference, and obtaining photomodulated reflectance (PMOR) offset curve measurement data and DC reflectance measurement data for the sample including the fully activated doping profile and for the reference. The method also includes determining values for the set of physical parameters of the doping profile based on both the photomodulated reflectance offset curve measurements and the DC reflectance measurements. | 06-20-2013 |
20130155572 | Metal-Insulator-Metal Stack and Method for Manufacturing the Same - A method for manufacturing a metal-insulator-metal (MIM) stack is described. The method includes forming a temporary stack by depositing a bottom electrode comprising at least one metal layer; depositing a dielectric comprising at least one layer of a dielectric material having a first dielectric constant value; and depositing a top electrode comprising at least one metal layer. The step of depositing the bottom and/or top electrode includes depositing a non-conductive metal oxide layer directly in contact with the dielectric; and after the step of depositing the bottom and/or top electrode's non-conductive metal oxide layer and the dielectric, subjecting the temporary stack to a stimulus, which transforms the non-conductive metal oxide into a thermodynamically stable oxide having conductive properties or into a metal, and the dielectric material into a crystalline form having a second dielectric constant value higher than the first dielectric constant value, thereby creating the final MIM stack. | 06-20-2013 |
20130161583 | Stacked RRAM Array With Integrated Transistor Selector - The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack. | 06-27-2013 |
20130161588 | Implant Free Quantum Well Transistor, Method for Making Such an Implant Free Quantum Well Transistor and Use of Such an Implant Free Quantum Well Transistor - An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region. | 06-27-2013 |
20130161696 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHODS FOR MANUFACTURING THEREOF - A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel. | 06-27-2013 |
20130161750 | N-Channel Laterally Diffused Metal-Oxide-Semiconductor Device - The disclosure relates to an n-channel laterally diffused metal-oxide-semiconductor device comprising an n+ source ( | 06-27-2013 |
20130164657 | EUV Photoresist Encapsulation - A method and system are described for performing extreme ultraviolet photolithographic processing. The method comprises obtaining a substrate comprising a hard mask and a patterned layer of extreme ultraviolet (EUV) photoresist formed above the hard mask, encapsulating the patterned layer of EUV photoresist by forming an encapsulating layer being one of a silicon-oxide, silicon-nitride, silicon-oxynitride, germanium-oxide, germanium-nitride, germanium-oxynitride, silicongermanium-oxide, silicongermanium-nitride, silicongermanium-oxynitride layer on the photoresist and dry etching of the substrate for patterning the hard mask. The encapsulation layer thereby is formed at a temperature below the weakening temperature Tg of the EUV photoresist by using a first precursor being one of the group of silicon-tetrahalogenide, silicon tetrahydride, germanium-tetrahalogenide, germanium tetrahydride, silicongermanium-tetrahalogenide or silicongermanium tetrahydride precursor and an oxygen precursor. | 06-27-2013 |
20130166616 | System and Method for Implementing a Multiplication - The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction. | 06-27-2013 |
20130173884 | PROGRAMMABLE DEVICE FOR SOFTWARE DEFINED RADIO TERMINAL - A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters. | 07-04-2013 |
20130176562 | METHOD AND APPARATUS FOR MEASURING CONCENTRATION OF BIOGENIC SUBSTANCE - A method for measuring a concentration of a biogenic substance in a living body includes steps of: preparing an apparatus including a light source, a substrate which has periodic metal structures and generates surface enhanced Raman scattering light by being irradiated with light from the light source, and spectroscopic means which disperses and detects the light, wherein the periodic metal structure is arranged with first and second distances in first and second direction respectively, the first distance is set to generate surface plasmon by matching a phase of the light from the light source, and the second distance is smaller than the first distance and is set between 300 nm and 350 nm; irradiating the substrate with the light from the light source to generate the surface enhanced Raman scattering; detecting the scattering with the spectroscopic means; and calculating the concentration of the biogenic substance based on the scattering. | 07-11-2013 |
20130177856 | METHOD FOR PRODUCING A LED DEVICE - A method is provided for producing a LED device, comprising a stack of layers comprising a light producing layer the light producing layer not being the top or bottom layer of the stack, wherein a layer at the top or bottom of the stack is subjected to a texturization aimed at enhancing the light extraction efficiency of the LED, wherein the texturization comprises the step of producing on the top or bottom surface a plurality of surface features, the surface features being arranged according to a pattern defined by starting from a regular pattern of features and subjecting each feature of the regular pattern to a deviation from the location in the regular pattern, the deviation being in a random direction and/or having a random amplitude. According to another embodiment, a random deviation is applied to one or more dimensions of the features in the regular pattern. | 07-11-2013 |
20130181301 | METHOD FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE FOLLOWING A REPLACEMENT GATE PROCESS - A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess. | 07-18-2013 |
20130187113 | Nonvolatile Memory Device Comprising a Metal-to-Insulator Transition Material - A nonvolatile memory device is disclosed comprising a metal-to-insulator transition material thermally coupled to a Peltier element. During programming, a selected current is flowing through the Peltier element, the level thereof determining whether the temperature of the Peltier element and hence of the thermally coupled metal-to-insulator transition material decreases or increases. In response to this temperature change, the metal-to-insulator transition material will change from one electrical conduction phase to another. The memory device is read by applying current through the metal-to-insulator transition material, the current level being selected to maintain the phase of the metal-to-insulator transition material. | 07-25-2013 |
20130187669 | Calibration of Micro-Mirror Arrays - A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use. | 07-25-2013 |
20130194577 | METHOD FOR DETERMINING AN ACTIVE DOPANT PROFILE - A method for determining an active dopant concentration profile of a semiconductor substrate based on optical measurements is disclosed. The active dopant concentration profile includes a concentration level and a junction depth. In one aspect, the method includes obtaining a photomodulated reflectance (PMOR) amplitude offset curve and a PMOR phase offset curve for the semiconductor substrate based on PMOR measurements, determining a decay length parameter based on a first derivative of the amplitude offset curve, determining a wavelength parameter based on a first derivative of the phase offset curve, and determining, from the decay length parameter and the wavelength parameter, the concentration level and the junction depth of the active dopant concentration profile. | 08-01-2013 |
20130198594 | Methods for Viterbi Decoder Implementation - Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget. | 08-01-2013 |
20130200320 | Self-Isolated Conductive Bridge Memory Device - A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator. | 08-08-2013 |