Patent application number | Description | Published |
20080290935 | APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLTAGE DOMAIN IS POWERED DOWN - An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down. | 11-27-2008 |
20090045847 | GENERIC FLEXIBLE TIMER DESIGN - One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits. | 02-19-2009 |
20140056050 | MEMORY CELL AND MEMORY - In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells. | 02-27-2014 |
20140125377 | DUAL FLIP-FLOP CIRCUIT - A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions. | 05-08-2014 |
20140129887 | FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN INPUT - A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal. | 05-08-2014 |
20140167828 | SMALL AREA LOW POWER DATA RETENTION FLOP - Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch. | 06-19-2014 |
20140169108 | MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES - Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal. | 06-19-2014 |
20140313817 | SRAM CORE CELL DESIGN WITH WRITE ASSIST - A static random access memory (SRAM) cell is disclosed. The SRAM cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted. | 10-23-2014 |
20140347916 | EIGHT TRANSISTOR (8T) WRITE ASSIST STATIC RANDOM ACCESS MEMORY (SRAM) CELL - Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch. | 11-27-2014 |