Patent application number | Description | Published |
20120162514 | DISPLAY APPARATUS, REMOTE CONTROLLER AND METHOD FOR CONTROLLING APPLIED THERETO - A display apparatus, a remote controller and a method for controlling applied thereto are provided. The display apparatus receives direction information regarding an orientation of the remote controller from the remote controller, and selects an area to be controlled by the remote controller from among a first area and a second area of a screen according to the direction information received from the remote controller. As a result, user is enabled to control different areas on the screen by appropriately moving the remote controller between different orientations. | 06-28-2012 |
20120167000 | DISPLAY APPARATUS AND METHOD FOR PLAYING MENU APPLIED THERETO - A display apparatus and a method for displaying a menu are provided. The display apparatus displays a content image on a first area of the entire screen area at a specific screen ratio and displays a menu comprising a plurality of pages on a second area corresponding to an area excluding the first area where the content image is displayed. Accordingly, the display apparatus may display a menu without blocking the content image or deteriorating quality of the content image. | 06-28-2012 |
20120185770 | METHOD FOR PROVIDING PLAYLIST, REMOTE CONTROLLER APPLYING THE SAME, AND MULTIMEDIA SYSTEM - A method for providing a playlist, a remote controller applying the same, and a multimedia system are provided. The method for providing a playlist includes displaying a plurality of content lists of a plurality of kinds of contents in which contents of a same kind are arranged together, the plurality of content lists being displayed on a first area of a screen, if at least two different kinds of contents are selected from the plurality of content lists in a selecting, collecting the selected contents of the at least two different kinds of contents, and generating and displaying a playlist including play information regarding the collected contents of the at least two different kinds of contents. | 07-19-2012 |
20120278719 | METHOD FOR PROVIDING LINK LIST AND DISPLAY APPARATUS APPLYING THE SAME - A method of providing a list of links on a display apparatus and a display apparatus are provided. The method includes recognizing a voice spoken by a user, searching, among links included in a web page being currently displayed on the display apparatus, for a link including an index which coincides with the voice spoken by the user and generating a list of one or more links, each including the index which coincides with the voice spoken by the user. | 11-01-2012 |
20130219283 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - The display apparatus includes: a display device; an image processor which processes an image to display the image on the display device; a communication unit which communicates with at least one first external device in which content data are stored and at least one second external device in which an application is installed to process the content data; and a controller which controls the image processor to communicate with the first and second external devices and display a user interface (UI) image corresponding to the content data and the application on the display device, and controls the processing operation of the application with respect to the content data through the UI image. | 08-22-2013 |
20130234958 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A display apparatus including: a communication unit which communicates with a peripheral device; an image processing unit which processes an image signal received from the peripheral device; a touch panel display unit which displays an image based on the image signal and comprises a touch sensing unit which detects touch input of a user; and a controller which controls a first mode and a second mode to operate according to a setting of the user, the first mode controlling the image processing unit so that the image based on the image signal received from the peripheral device is displayed on the touch panel display unit and the second mode controlling the image processing unit and the touch panel display unit so that a graphic user interface (GUI) is displayed on the touch panel display unit and the touch input for controlling the peripheral device is received using the GUI. | 09-12-2013 |
20140303958 | CONTROL METHOD OF INTERPRETATION APPARATUS, CONTROL METHOD OF INTERPRETATION SERVER, CONTROL METHOD OF INTERPRETATION SYSTEM AND USER TERMINAL - A method of controlling an interpretation apparatus is provided. The control method includes collecting a voice of a speaker in a first language in order to generate voice data, extracting voice attribution information of the speaker from the generated voice data, and transmitting to an external apparatus text data in which the voice of the speaker included in the generated voice data is translated in a second language, together with the extracted voice attribute information. The text data translated in the second language is generated by recognizing the voice of the speaker included in the generated voice data, converting the recognized voice of the speaker into the text data, and translating the converted text data in the second language. | 10-09-2014 |
Patent application number | Description | Published |
20110304763 | IMAGE SENSOR CHIP AND CAMERA MODULE HAVING THE SAME - An image sensor chip, a camera module, and devices incorporating the image sensor chip and camera module include a light receiving unit on which light is incident, a logic unit provided to surround the light receiving unit, and an electromagnetic wave shielding layer formed on the logic unit and not formed on the light receiving unit. | 12-15-2011 |
20110316144 | FLEXIBLE HEAT SINK HAVING VENTILATION PORTS AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure. | 12-29-2011 |
20130135823 | SEMICONDUCTOR PACKAGES USABLE WITH A MOBILE DEVICE - A semiconductor package usable with a mobile device includes a circuit board including conductive wirings therein and contact terminals on a rear surface thereof, an integrated circuit chip positioned on a front surface of the circuit board and electrically connected to the conductive wirings, a cover including at least an opening, and to cover the integrated circuit chip such that a flow space is provided around the integrated circuit chip and the opening communicates with the flow space, and an air flow generator positioned on the cover to generate a compulsory air flow through the flow space and the opening, thereby dissipating heat out of the semiconductor package from the integrated circuit chip by the compulsory air flow. | 05-30-2013 |
20140159185 | IMAGE SENSOR PACKAGE - An image sensor package including a PCB including bonding areas, an image sensor including bonding pads on edge portions thereof on the PCB, bonding wires connecting the bonding pads with the bonding areas, an insulating adhesion film attaching the bonding wires to the bonding pads on the edge portions of the image sensor, a heat spread pattern spaced apart from the bonding wires and the image sensor on the insulating adhesion film, a supporting holder spaced apart from the edge portions of the image sensor, encloses the image sensor, contacts a top surface of the heat spread pattern and the PCB, and includes a supporting portion at an upper portion thereof, and a transparent cover covering the image sensor on the supporting portion of the supporting holder and spaced apart from the top surface of the image sensor is provided. | 06-12-2014 |
20140239300 | SEMICONDUCTOR TEST DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor. | 08-28-2014 |
20140254092 | SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A semiconductor package and an electronic system including the same include a package board having an electric circuit pattern. A semiconductor chip is mounted on the package board and electrically connected with the circuit pattern of the package board. A non-contact temperature detector is provided with the semiconductor package and detects a temperature of an external heat source without making contact with the external heat source. A temperature controller controls the semiconductor chip according to the temperature of the external heat source that is detected by the non-contact temperature detector. | 09-11-2014 |
20140264339 | HEAT SLUG HAVING THERMOELECTRIC ELEMENTS AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - In a heat slug and a semiconductor package including the same, the heat slug includes a thermal conductive body having an active face and a dissipating face opposite to the active face, a dielectric layer covering the active face of the body, at least one thermoelectric element arranged on the dielectric layer and a conductive pattern arranged on the dielectric layer and electrically connected to the thermoelectric element. The electrical characteristics of the thermoelectric element are interacted with heat generated from a heat source. | 09-18-2014 |
Patent application number | Description | Published |
20110228581 | STACKED MEMORY DEVICE AND METHOD OF REPAIRING SAME - A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield. | 09-22-2011 |
20110228582 | STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME - A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit. | 09-22-2011 |
20110231735 | STACKED SEMICONDUCTOR MEMORY DEVICE AND RELATED ERROR-CORRECTION METHOD - A stacked semiconductor memory device comprises an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word. | 09-22-2011 |
20110286254 | Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. | 11-24-2011 |
20110305059 | Semiconductor Memory Devices - Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer. | 12-15-2011 |
20110305100 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers | 12-15-2011 |
20120020142 | RESISTIVE MEMORY - Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current. | 01-26-2012 |
20120063194 | SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME - Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion. | 03-15-2012 |
20120063196 | RESISTIVE MEMORY DEVICE AND METHOD OF CONTROLLING REFRESH OPERATION OF RESISTIVE MEMORY DEVICE - A resistive memory device comprises a memory cell array comprising a plurality of memory units. The memory device performs a refresh read operation to check a condition of each of the memory units. Then, it determines whether to refresh each memory unit based on data read by performing the refresh read operation, and refreshes the memory unit according to a result of the determination. The refresh read operation uses a reference resistance with a smaller margin from a resistance distribution than a normal read operation. | 03-15-2012 |
20120087177 | SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING - A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage. | 04-12-2012 |
20120099364 | RESISTIVE MEMORY DEVICES, INITIALIZATION METHODS, AND ELECTRONIC DEVICES INCORPORATING SAME - A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells. | 04-26-2012 |
20120106281 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS - A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal. | 05-03-2012 |
20120182786 | BIDIRECTIONAL RESISTIVE MEMORY DEVICES USING SELECTIVE READ VOLTAGE POLARITY - A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell. | 07-19-2012 |
20120212989 | MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors. | 08-23-2012 |
20120230139 | SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME - A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell. | 09-13-2012 |
20120300568 | Method of Refreshing a Memory Device, Refresh Address Generator and Memory Device - A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging. | 11-29-2012 |
20130039135 | MEMORY DEVICE FOR MANAGING TIMING PARAMETERS - A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types. | 02-14-2013 |
20130051133 | ANTI-FUSE CIRCUIT USING MTJ BREAKDWON AND SEMICONDUCTOR DEVICE INCLUDING SAME - An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses. | 02-28-2013 |
20130055048 | BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM - A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information. | 02-28-2013 |
20130058145 | MEMORY SYSTEM - A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells. | 03-07-2013 |
20130064008 | DATA READ CIRCUIT, NONVOLATILE MEMORY DEVICE COMPRISING DATA READ CIRCUIT, AND METHOD OF READING DATA FROM NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit. | 03-14-2013 |
20130148429 | MEMORY DEVICE, METHOD OF PERFORMING READ OR WRITE OPERATION AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided. | 06-13-2013 |
20130237019 | STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME - A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit. | 09-12-2013 |
20130279283 | MEMORY DEVICES AND MEMORY CONTROLLERS - A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals. | 10-24-2013 |
20130282973 | VOLATILE MEMORY DEVICE AND A MEMORY CONTROLLER - A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows. | 10-24-2013 |
20130329478 | Semiconductor Devices Having a Three Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. | 12-12-2013 |
20140092680 | MULTIPLE WELL BIAS MEMORY - A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage. | 04-03-2014 |
20140112086 | REFRESH METHOD, REFRESH ADDRESS GENERATOR, VOLATILE MEMORY DEVICE INCLUDING THE SAME - A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device. | 04-24-2014 |
20140169086 | COMMON SOURCE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units. | 06-19-2014 |
Patent application number | Description | Published |
20110215421 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer. | 09-08-2011 |
20120139028 | SEMICONDUCTOR MEMORY DEVICE AND EMTHOD OF FORMING THE SAME - A semiconductor memory device includes a device isolation pattern defining an active region of a substrate, a buried gate electrode extending longitudinally in a given direction across the active region, a first impurity region and a second impurity region disposed along respective sides of the buried gate electrode, a conductive pad disposed on the substrate and electrically connected to the first impurity region, a first contact plug disposed on the substrate and electrically connected to the second impurity doping region, and a second contact plug disposed on the pad. | 06-07-2012 |
20120164830 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F | 06-28-2012 |
20120214316 | SEMICONDUCTOR DEVICES HAVING PLANARIZED INSULATION LAYERS AND METHODS OF FABRICATING THE SAME - A semiconductor device and a method of fabricating a semiconductor device including a step of providing a substrate having a first region and a second region adjacent to each other, a step of forming a structure on the substrate in the first region, the structure including a top surface and a sidewall, a step of forming a first insulation layer on the substrate including the structure, the first insulation layer including a first top surface in the first region, an inclined sidewall on the sidewall of structure, and a second top surface in the second region, a step of forming a second insulation layer on the first insulation layer, and a step of planarizing the second and first insulation layers to form a common planarized surface. | 08-23-2012 |
20120231601 | Methods of fabricating a semiconductor device having metallic storage nodes - The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven. | 09-13-2012 |
20130240959 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line. | 09-19-2013 |
20140332905 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer. | 11-13-2014 |
Patent application number | Description | Published |
20080220375 | Methods of reworking a semiconductor substrate and methods of forming a pattern in a semiconductor device - In a method of reworking a substrate, an organic anti-reflection coating (ARC) layer is formed on the substrate having an amorphous carbon pattern. A photoresist pattern is formed on the organic ARC layer. The photoresist pattern is entirely exposed when the photoresist pattern has a selected level of defects, and then the photoresist pattern is removed by a developing process. The substrate may be reworked without damaging the organic ARC layer, and the amorphous carbon pattern may include an alignment key and/or an overlay key. | 09-11-2008 |
20080264566 | Apparatus and method for removing a photoresist structure from a substrate - In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water vapor, and a second space connected to the first space so that the water vapor is supplied to and partially condensed into liquid water on one or more walls of the first space. Ozone gas and water vapor without liquid water may be supplied to the second space to form the mixture therein. The showerhead may be heated to vaporize the liquid water on a given surface of the first space. | 10-30-2008 |
20100093165 | Method of fabricating integrated circuit semiconductor device having gate metal silicide layer - Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes. | 04-15-2010 |
20100173470 | Methods of forming a silicon oxide layer and methods of forming an isolation layer - In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked. | 07-08-2010 |
20110171882 | CHEMICAL-MECHANICAL POLISHING APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICES - A chemical-mechanical polishing (CMP) apparatus for manufacturing a semiconductor device. The apparatus includes: a spin chuck for supporting and rotating a semiconductor wafer; a polisher comprising a polishing pad for planarizing a surface of the semiconductor wafer, the polisher moving along the surface of the semiconductor wafer by a polishing arm; and a polisher supporting device for supporting the polisher and maintaining the polisher in a horizontal state, while polishing an edge part of the surface of the semiconductor wafer, in order to improve polishing uniformity of a center part and the edge part of the semiconductor wafer. Accordingly, polishing uniformity of the center part and edge part of the semiconductor wafer may be improved, and a height of the polisher supporting device may be optimized according to a polishing degree. Also, the polisher may be easily supported, wear and tear of the support head may be minimized, and the support head may function as a conditioner. | 07-14-2011 |
20110284968 | SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a recessed portion including at least two oblique side surfaces and a first bottom surface therebetween, a gate insulating layer formed on the recessed portion, a gate electrode formed on the gate insulating layer, a channel region below the gate electrode in the semiconductor substrate, and gate spacers formed on side surfaces of the gate electrode, wherein both the bottom surface and the side surfaces of the recessed portion include flat surfaces. A method of manufacturing a semiconductor device comprising the steps of forming a recess portion including at least two oblique side surfaces and a bottom surface therebetween in a semiconductor substrate, forming a gate insulating layer formed on the recessed portion, forming a gate electrode formed on the gate insulating layer, forming a channel region below the gate electrode in the semiconductor substrate, and forming gate spacers formed on side surfaces of the gate electrode. | 11-24-2011 |
20120025283 | MEMORY DEVICE - In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced. | 02-02-2012 |
20130341710 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth. | 12-26-2013 |
Patent application number | Description | Published |
20120141302 | OIL PUMP SYSTEM FOR AUTOMATIC TRANSMISSION - A hydraulic pump system for an automatic transmission has the advantages of preventing excessive power loss and durability deterioration. The hydraulic pump system may include a first hydraulic pump that generates a first hydraulic pressure to supply a low pressure portion with the first hydraulic pump, a second hydraulic pump that receives the first hydraulic pressure to generate a second hydraulic pressure higher than the first hydraulic pressure and supplies a high pressure portion with the second hydraulic pressure, and a drive portion that rotates a drive shaft that integrally connects the first hydraulic pump with the second hydraulic pump. | 06-07-2012 |
20130071263 | OIL SUPPLY APPARATUS FOR A VEHICLE - An oil supply apparatus for a vehicle may include an oil pump, a first rotary member provided to the oil pump such that the oil pump may be rotatably operated by the first rotary member, a second rotary member restricted from rotating with respect to the first rotary member in a first direction, the second rotary member being allowed to rotate with respect to the first rotary member in a second direction opposite to the first direction, and a third rotary member allowed to rotate in the first direction with respect to the first rotary member, the third rotary member being restricted from rotating with respect to the first rotary member in the second direction opposite to the first direction, wherein the second rotary member and the third rotary member may be respectively connected to power sources providing drive forces in directions opposite to each other. | 03-21-2013 |
20130133320 | HYDRAULIC PRESSURE CONTROL APPARATUS FOR AUTOMATIC TRANSMISSION - A hydraulic pressure control apparatus may include an oil tank, a first hydraulic pump receiving oil from the oil tank generating a low pressure, a second hydraulic pump receiving the low pressure and generating a high pressure, a torque converter and a lubrication portion receiving the low pressure, a powertrain receiving the high pressure, a pump connecting line connecting the first hydraulic pump with the second hydraulic pump, a first bypass line adapted to supply hydraulic pressure from the oil tank to the second hydraulic pump by detouring around the first hydraulic pump, and a second bypass line bifurcated from the pump connecting line so as to supply hydraulic pressure to the powertrain by detouring around the second hydraulic pump, wherein the first bypass line and the second bypass line respectively include a check valve and are selectively opened/closed by operation of each check valve. | 05-30-2013 |
20130133766 | HYDRAULIC PRESSURE CONTROL APPARATUS FOR AUTOMATIC TRANSMISSION - A hydraulic pressure control apparatus for an automatic transmission may include an oil tank, a first hydraulic pump fluid-connected with the oil tank for generating a first hydraulic pressure, a second hydraulic pump fluid-connected with the first hydraulic pump for generating a second hydraulic pressure higher than the first pressure, a torque converter and a lubrication portion fluid-connected to a first low pressure supply line to receive the first hydraulic pressure, a first high pressure supply line fluid-connected to the second hydraulic pump and to a powertrain, a switching valve bifurcated from the first low pressure supply line and fluid-connected to the first hydraulic pump and both the torque converter and the lubrication portion, and a feedback line fluid-connected to the first high pressure supply line to the switching valve so as to selectively open or close the switching valve according to the second hydraulic pressure. | 05-30-2013 |
20130134004 | HYDRAULIC PRESSURE CONTROL APPARATUS FOR AUTOMATIC TRANSMISSION AND CONTROL METHOD THEREOF - A hydraulic pressure control apparatus for an automatic transmission may include a first hydraulic pump connected with an oil tank to receive oil from the oil tank, having a first motor, and adapted to generate a low pressure through an operation of the first motor, a second hydraulic pump connected with the first hydraulic pump to receive the low pressure, having a second motor, and adapted to generate a high pressure through an operation of the second motor, a first regulating valve adapted to receive the low pressure from the first hydraulic pump and to regulate a first operating pressure to supply to the torque converter, and a second regulating valve adapted to receive the high pressure from the second hydraulic pump and to regulate a second operating pressure to supply to the powertrain. | 05-30-2013 |
20130136623 | SYSTEM FOR CONTROLLING AN ELECTRIC OIL PUMP - A system for accurately and reliably controlling an electric oil pump includes a control portion adapted to control rotation speed of the motor of the electric oil pump, a regulator valve including a valve body provided with a plurality of ports, a valve spool inserted in the valve body and an elastic member adapted to apply elastic force to the valve spool, and a switch mounted on one side of the valve body including first and second contact points, wherein the control portion increases the rotation speed of the motor when the switch is on and maintains the rotation speed of the motor when the switch is off. | 05-30-2013 |
20130269802 | HYDRAULIC PRESSURE CONTROL APPARATUS FOR AUTOMATIC TRANSMISSION AND CONTROL METHOD THEREOF - A hydraulic pressure control apparatus for an automatic transmission may include a first hydraulic pump connected with an oil tank to receive oil from the oil tank, having a first motor, and adapted to generate a low pressure through an operation of the first motor, a second hydraulic pump connected with the first hydraulic pump to receive the low pressure, having a second motor, and adapted to generate a high pressure through an operation of the second motor, a first regulating valve adapted to receive the low pressure from the first hydraulic pump and to regulate a first operating pressure to supply to the torque converter, and a second regulating valve adapted to receive the high pressure from the second hydraulic pump and to regulate a second operating pressure to supply to the powertrain. | 10-17-2013 |
20130300413 | METHOD AND APPARATUS FOR GENERATING MAGNETIC RESONANCE IMAGE - A method of generating a magnetic resonance image includes: generating composite data by using a plurality of data sets acquired from a plurality of coils, based on coil characteristics of the plurality of coils; generating first interpolation data by interpolating the composite data; generating a plurality of filtered data sets by filtering the first interpolation data with respect to a plurality of frequency bands; and generating the magnetic resonance image by using the plurality of filtered data sets. | 11-14-2013 |
20130301891 | METHOD AND APPARATUS FOR GENERATING MAGNETIC RESONANCE IMAGE - A method of generating a magnetic resonance image includes: generating pieces of first interpolation data by interpolating pieces of data obtained from each of the plurality of coils; generating pieces of weighted data by weighting the pieces of first interpolation data with respect to a plurality of frequency bands; and obtaining the magnetic resonance image corresponding to a subject by using the pieces of weighted data. | 11-14-2013 |
20140191753 | METHOD AND APPARATUS FOR OBTAINING MAGNETIC RESONANCE IMAGE - An MRI method includes: defining image regions on an object; setting imaging conditions for the defined image regions; and acquiring MR images for the image regions according to the set imaging conditions. The imaging conditions may be set by displaying information about the defined image regions and setting the imaging conditions for the image regions based on the displayed information. | 07-10-2014 |
Patent application number | Description | Published |
20110164394 | DISPLAY DEVICE - A display device having a compact structure includes a main board and an inverter board of the display device connected to each other. A bracket supports the main board and the inverter board. The bracket includes a shielding part to block electromagnetic waves, an inverter board holding part to allow the inverter board to be easily seated on the bracket, and a support and fixing part to support and fix the bracket. Further, a front cover and a back cover are connected in a snap-fit manner, and a bottom chassis includes a cable receipt groove to organize the internal wiring of the display device. | 07-07-2011 |
20120163645 | DISPLAY APPARATUS - A display apparatus is provided which includes a display panel, a front cover which accommodates a front of the display panel, the front cover being provided with a front cover extension formed at one side, a rear cover coupled to the front cover, the rear cover being provided with a rear cover extension corresponding to the front cover extension of the front cover, a bracket panel mounted between the display panel and the rear cover to support the display panel, the bracket panel including a coupling part coupled to the rear of the display panel and a support part which extends from a lower part of the coupling part, a stand unit coupled to the lower end of the support part of the bracket panel, the stand unit having a main circuit board mounted therein, and a hinge fixed to the support part of the bracket panel. | 06-28-2012 |
20140055960 | DISPLAY DEVICE - A display device having a compact structure includes a main board and an inverter board of the display device connected to each other. A bracket supports the main board and the inverter board. The bracket includes a shielding part to block electromagnetic waves, an inverter board holding part to allow the inverter board to be easily seated on the bracket, and a support and fixing part to support and fix the bracket. Further, a front cover and a back cover are connected in a snap-fit manner, and a bottom chassis includes a cable receipt groove to organize the internal wiring of the display device. | 02-27-2014 |
20140192270 | SUPPORT FRAME AND DISPLAY DEVICE INCLUDING THE SAME - A television apparatus comprises a support frame and a leg member extending from the support frame to support the support frame in an inclined orientation. The television apparatus further comprises a display panel unit having a chassis movably mounted to the support frame via a first coupling assembly mounted between a right side edge portion of the chassis and a right side section of the support frame, and a second coupling assembly mounted between a left side edge portion of the chassis and a left side section of the support frame. | 07-10-2014 |
20150043136 | DISPLAY APPARATUS - Disclosed herein is a display apparatus which may be selectively used in a flat state or a curved state. The display apparatus includes a display module that displays an image and is provided to be bent, and a bending device that is provided to enable the display module to be transformed into a flat state or a curved state. Here, the bending device includes a frame that is provided at a rear side of the display module and a hinge unit that connects between the frames and is provided to enable curvature of the frame to vary by torque. | 02-12-2015 |
Patent application number | Description | Published |
20120083301 | APPARATUS AND METHOD FOR COMMUNICATING IN A NETWORK IN WHICH INTERFERENCE EXISTS BETWEEN WIRELESS COMMUNICATION SYSTEMS - An apparatus and method are provided for communicating in a network in which interference exists between wireless communication systems. The apparatus includes multiple transceivers for individually communicating with base stations of the multiple wireless communication systems; and a controller for negotiating with at least one of the base stations, setting a non-communication period with a negotiated base station, and communicating with the negotiated base station during the non-communication period, based on whether an interference level between wireless signals communicated through the multiple transceivers falls within a predetermined range. | 04-05-2012 |
20120170482 | APPARATUS AND METHOD FOR TRANSMITTING DATA IN LOW-FREQUENCY BAND IN HUMAN BODY COMMUNICATION SYSTEM, AND THE HUMAN BODY COMMUNICATION SYSTEM - The present invention proposes a method for transmitting data considering a non-contact state of a human body, while selecting a central frequency in various ranges in the human body communication system. To this end, a first embodiment of the present invention proposes a human body communication system in which a central frequency can be simply moved, and specifically, proposes a data transmission apparatus comprising a frequency shifter which shifts the output of a multiplexer into a specified frequency so as to enable the central frequency to be moved. In addition, a second embodiment of the present invention proposes a human body communication system which controls not only central frequency selection and transmission band minimization, but also a data rate, modulation, etc, and thus can perform stable communication in a non-contact state of a human body. Through this, it is possible to maximize the band efficiency, and to transmit data considering a non-contact state of a human body. | 07-05-2012 |
20130051292 | COMMUNICATION APPARATUS AND METHOD USING PSEUDO-RANDOM CODE - According to the present invention, a communication apparatus comprises: a preamble generator which generates a pseudo-random code; a band shaping code generator which generates a band shaping code having a higher frequency than the pseudo-random code; a calculator which performs a calculation of the pseudo-random code and the band shaping code and outputs a preamble obtained through the calculation; and a multiplexer which multiplexes the preamble for synchronization with a second communication apparatus, a header, and data, and outputs a data frame obtained through the multiplexing. | 02-28-2013 |
20130052974 | APPARATUS FOR RECEIVING ANALOG BASEBAND SIGNAL - Provided is a receiving apparatus for processing an analog baseband signal in an information terminal that communicates using a dielectric. The receiving apparatus includes an electrode for receiving an electric-field signal; a first gain adjuster for gain adjustment by amplifying the received signal; a channel selection filter for selecting a signal corresponding to a receive channel bandwidth from the gain-adjusted signal; a second gain adjuster for gain adjustment by amplifying the selected signal; a comparator for converting a signal output from the second gain adjuster into a digital signal; an oversampler for oversampling the digital signal at a frequency f | 02-28-2013 |
20140286207 | APPARATUS AND METHOD OF PERFORMING CHANNEL ESTIMATION IN A WIRELESS COMMUNICATION SYSTEM - A method and apparatus of performing channel estimation in a wireless communication system are provided. The method includes determining a channel response value of a midamble sequence included in a downlink slot, detecting a first channel response value of a window allocated to a user and a second channel response value of a window allocated to at least one other user based on the channel response value of the midamble sequence, determining whether a Base Station (BS) of a current cell uses beamforming based on the first and second channel response values, and combining the first and second channel response values and using the combined channel response value for signal detection if it is determined that the BS does not use beamforming. | 09-25-2014 |
20150045087 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION IN WIRELESS COMMUNICATION SYSTEM - An apparatus and a method for reducing power consumption in a wireless communication system are provided. The apparatus includes an antenna, a Radio Frequency (RF) module, a first amplifier, an external power amplifier, and a controller. The RF module converts a baseband transmission signal to an RF signal. The first amplifier amplifies power of the RF signal inside the RF module. The external power amplifier amplifies power of an output signal of the first amplifier. When a transmission power level of a transmission signal is equal to or less than a maximum output level of the first amplifier, the controller controls to transmit the transmission signal amplified by the first amplifier via the antenna. When the transmission power level of the transmission signal is equal to or greater than the maximum output level of the first amplifier, the controller controls to transmit a transmission signal amplified by the external power amplifier via the antenna. | 02-12-2015 |
Patent application number | Description | Published |
20090021649 | VIDEO APPARATUS AND METHOD FOR SUPPLYING POWER THEREOF - A video apparatus and a method for supplying power thereof are provided. The video apparatus includes a video processor which processes a video signal, a transceiver which receives a communication connection signal from an exterior apparatus, and a controller which allows power to be supplied to the video processor to generate the processed video signal to be output to the exterior apparatus through the transceiver, if the communication connection signal is received through the transceiver. | 01-22-2009 |
20100009629 | WIRELESS COMMUNICATION METHOD, AND WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION SYSTEM USING THE SAME - A wireless communication method, and a wireless communication apparatus and wireless communication system using the same. The wireless communication method includes pairing with a specific device, extracting a media access control (MAC) address of the specific device, and communicating with the specific device. Accordingly, even when a MAC address of a counterpart device is not known, pairing with the counterpart device can be performed without interference with other devices. | 01-14-2010 |
20110140833 | REMOTE CONTROL APPARATUS AND METHOD THEREOF - Provided are an apparatus, system and method thereof for a remote control including a radio frequency (RF) antenna operable to transmit an RF signal to a first device; an infrared (IR) transmitter operable to transmit an IR signal to a second device; a user input unit operable to receive an input command from a user; a controller which determines if the input command is received, and if the input command is received, the controller controls the RF antenna to transmit the RF signal to the first device and the controller controls the IR transmitter to transmit the IR signal to the second device. | 06-16-2011 |
20110181708 | DISPLAY DEVICE AND METHOD OF DRIVING THE SAME, AND SHUTTER GLASSES AND METHOD OF DRIVING THE SAME - Disclosed is a display device using three-dimensional (3D) shutter glasses including a left shutter and a right shutter, the display device including: a signal receiving unit which receives an image signal including a left image and a right image; a signal processing unit which processes the image signal received by the signal receiving unit; a display unit which displays a 3D image according to the processed image signal; a synchronization signal receiving unit which receives a synchronization signal for the left and right images from the 3D glasses; and a controller which controls the signal processing unit to alternately display the left and right images according to the synchronization signal corresponding to opening and closing of the left shutter and the right shutter. | 07-28-2011 |
20110234771 | APPARATUS, METHOD AND SYSTEM FOR SYNCHRONIZATION AND 3D DISPLAY APPARATUS USING THE SAME - Apparatus, method, and system for synchronization and a three-dimensional (3D) display apparatus using the same are provided. The 3D display apparatus includes: a power generator which generates power based on a received alternating current (AC) power signal, a detector which detects zero crossing points of time of the received AC power signal, and a controller which generates a reference signal based on the detected zero crossing points of time and transmits the reference signal to at least one other 3D display apparatus. | 09-29-2011 |
20110248859 | METHOD OF PROVIDING 3D IMAGE AND 3D DISPLAY APPARATUS USING THE SAME - Provided are a three dimensional (3D) display apparatus, a method of setting up a graphic user interface (GUI) thereof, and 3D glasses. The method of providing a GUI of the 3D display apparatus operating in association with the 3D glasses includes receiving a signal including battery information from the 3D glasses, generating a GUI related to the battery information of the 3D glasses, using the battery information contained in the received signal, and displaying the generated GUI on a screen of the 3D display apparatus. | 10-13-2011 |
20110254933 | SHUTTER GLASSES, DISPLAY APPARATUS INCLUDING THE SAME, AND CONTROL METHOD THEREOF - Provided are a display apparatus for transmitting a sync signal, shutter glasses, and a method of controlling the same. The display apparatus includes: a video signal processor which processes a predetermined three-dimensional (3D) video signal to be displayed on a display unit; a communication unit which communicates with the shutter glasses; and a sync signal generator which generates a sync signal to open and close shutters of the shutter glasses in response to the 3D video signal, the generated sync signal including error-correction information for correcting an error that causes malfunction of the shutter glasses, wherein the sync signal generator transmits, to the shutter glasses, the generated sync signal including the error-correction information through a communication unit. | 10-20-2011 |
20110254934 | DISPLAY APPARATUS, 3D GLASSES, AND DISPLAY SYSTEM INCLUDING THE SAME - A display apparatus, three-dimensional (3D) glasses, and a display system including the display apparatus and the 3D glasses are provided. The 3D glasses which interwork with an external display apparatus include: a wireless receiver which receives a sync signal and audio signals from the external display apparatus; a shutter driver which drives shutters according to the received sync signal; and an audio output part which processes and outputs the received audio signal. Thus, users can individually enjoy contents without interfering with one another by selecting and listening to audio corresponding to an image viewed through the display apparatus. | 10-20-2011 |
20120014299 | ACCESS POINT AND METHOD FOR CONNECTING WIRELESS COMMUNICATION - An access point and a method for connecting wireless communication thereof are provided. The method includes, if a connecting device is connected to the access point, registering information of the connecting device, if the connecting device transmits a first signal in response to a beacon message of the access point after having been disconnected from the access point and connected to a host device, determining whether the connecting device is already registered using the first signal, and, if it is determined that the connecting device is already registered, connecting to the host device via the wireless communication connection. | 01-19-2012 |
20120069161 | 3D GLASSES AND 3D DISPLAY APPARATUS USING IR SIGNAL AND RF SIGNAL - Three dimensional (3D) glasses and a 3D display apparatus are provided. The 3D glasses receive a sync signal from the 3D display apparatus through at least one of an infrared signal and a radio frequency signal. | 03-22-2012 |
20120169852 | DISPLAY APPARATUS AND SYSTEM - Disclosed are a display apparatus and a system including the same. A 3-dimensional (3D) display apparatus includes a display unit; a video signal processor which extracts frame sync signals corresponding to a left-eye image and a right-eye image from a predetermined 3D video signal, and processes the left-eye image and the right-eye image to be alternately displayed on the display unit; and a first communication unit which communicates with an external 3D display apparatus, and transmits a display sync signal based on the extracted frame sync signal to the external 3D display apparatus so that a 3D image displayed in the external 3D display apparatus can be synchronized with order of the left-eye image and the right-eye image displayed on the display unit. | 07-05-2012 |
20120169854 | DISPLAY APPARATUS, 3D GLASSES, AND CONTROL METHOD THEREOF - Disclosed are a display apparatus, three-dimensional (3D) glasses and a control method thereof. The method of controlling three-dimensional (3D) glasses for a display apparatus includes: synchronizing clocks for communicating with the 3D glasses; generating drive timing information for driving shutters of the 3D glasses from the synchronized clocks and a frame sync signal of a displayed image; and transmitting a glasses control message, comprising the drive timing information, to the 3D glasses. | 07-05-2012 |
20120174088 | ELECTRONIC DEVICE AND METHOD FOR UPDATING SOFTWARE THEREOF - Disclosed are an electronic device and a method for updating software thereof. The electronic device includes: a communication unit which includes predetermined software needed for communicating with an exterior; a first storage which stores user information set up in the electronic device; a user input unit; and a controller which updates the software with an update file needed for updating the software and sets up the stored user information again in the communication unit if receiving update instruction for the software through the user input unit. | 07-05-2012 |
20120307710 | REPEATER, BROADCAST TRANSMITTING SYSTEM AND METHOD FOR RELAYING BROADCAST SIGNAL - A repeater, broadcast transmitting system, and method for relaying a broadcast signal between a gateway apparatus and a client apparatus are provided. The repeater includes a first interface which is configured to be connected to a gateway apparatus via a Wi-Fi communication protocol and is configured to receive a broadcast signal from the gateway apparatus; and a second interface which is configured to be connected to a client apparatus via the Wi-Fi communication protocol and is configured to transmit the broadcast signal to the client apparatus, wherein the first interface and the second interface use different frequency bands. | 12-06-2012 |
20120307711 | REPEATER - A repeater and method of controlling thereof are provided. The repeater includes: a first interface unit which is configured to be connected to a gateway apparatus via a Wi-Fi communication protocol; and a second interface unit which is configured to be connected to a client device via the Wi-Fi communication protocol, wherein at least one of the first and second interface units comprises a filter which filters different frequency bands. | 12-06-2012 |
20130235052 | DISPLAY APPARATUS, 3D GLASSES, AND CONTROL METHOD THEREOF - Disclosed are a display apparatus, three-dimensional (3D) glasses and a control method thereof. The method of controlling three-dimensional (3D) glasses for a display apparatus includes: synchronizing clocks for communicating with the 3D glasses; generating drive timing information for driving shutters of the 3D glasses from the synchronized clocks and a frame sync signal of a displayed image; and transmitting a glasses control message, comprising the drive timing information, to the 3D glasses. | 09-12-2013 |
20140307725 | ACCESS POINT AND METHOD FOR CONNECTING WIRELESS COMMUNICATION - An access point and a method for connecting wireless communication thereof are provided. The method includes, if a connecting device is connected to the access point, registering information of the connecting device, if the connecting device transmits a first signal in response to a beacon message of the access point after having been disconnected from the access point and connected to a host device, determining whether the connecting device is already registered using the first signal, and, if it is determined that the connecting device is already registered, connecting to the host device via the wireless communication connection. | 10-16-2014 |
20140313297 | DISPLAY APPARATUS, 3D GLASSES, AND DISPLAY SYSTEM INCLUDING THE SAME - A display apparatus, three-dimensional (3D) glasses, and a display system including the display apparatus and the 3D glasses are provided. The 3D glasses which interwork with an external display apparatus include: a wireless receiver which receives a sync signal and audio signals from the external display apparatus; a shutter driver which drives shutters according to the received sync signal; and an audio output part which processes and outputs the received audio signal. Thus, users can individually enjoy contents without interfering with one another by selecting and listening to audio corresponding to an image viewed through the display apparatus. | 10-23-2014 |
Patent application number | Description | Published |
20120007208 | Semiconductor Devices and Methods of Manufacturing the Same - Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include first and second active patterns. The second active patterns may protrude from the first active patterns. The semiconductor devices may also include a device isolation pattern between each of the first active patterns. The semiconductor devices may further include a sidewall mask on the first active patterns and the second active patterns. The semiconductor devices may additionally include a buried conductive pattern on the device isolation pattern. | 01-12-2012 |
20120086065 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor. | 04-12-2012 |
20120086066 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern. | 04-12-2012 |
20120156844 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS AND METHODS OF FABRICATING THE SAME - Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided. | 06-21-2012 |
20130001675 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars. | 01-03-2013 |
20130087842 | SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - According to example embodiments, a semiconductor device includes a lower active portion protruding from a substrate, an active pillar protruding from the lower active portion, a surround gate electrode surrounding the active pillar, a buried bit line extending along a first direction and being on the lower active portion and electrically connected to the lower active portion, and a contact gate electrode contacting both the surround gate electrode and a word line extending a second direction crossing the first direction. | 04-11-2013 |
20130171783 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR - A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern. | 07-04-2013 |
20130260531 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring. | 10-03-2013 |
20130292847 | Semiconductor Devices and Methods of Manufacturing the Same - A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad. | 11-07-2013 |
20140117492 | SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACTIVE REGION, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A RECESSED ACTIVE REGION - Semiconductor devices are provided. Each of the semiconductor devices may include a substrate including an active region that includes first and second regions. Each of the semiconductor devices may include a device isolation layer between the first and second regions of the active region. Each of the semiconductor devices may include a contact hole defined by recessed portions of the device isolation layer and the first region of the active region, respectively. Moreover, a topmost surface of the first region of the active region may define a bottommost portion of the contact hole. Related methods of forming semiconductor devices are also provided. | 05-01-2014 |
20140159148 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions. | 06-12-2014 |
20140203357 | Semiconductor Device and Method of Manufacturing the Same - According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched. A top surface of the etched portion of the substrate between the grooves is higher than a bottom surface of the groove. A conductive layer is formed to fill the grooves. The conductive layer is etched to form conductive patterns in the grooves, respectively. | 07-24-2014 |
20140246782 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact. | 09-04-2014 |
20140327087 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions. | 11-06-2014 |
20150055401 | SEMICONDUCTOR DEVICES INCLUDING DUAL GATE ELECTRODE STRUCTURES AND RELATED METHODS - A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed. | 02-26-2015 |
Patent application number | Description | Published |
20090087962 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY - In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region. | 04-02-2009 |
20110221010 | SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY - A semiconductor includes a plurality of active regions that are separated from each other on a substrate by a device isolation layer and extend in a first direction, the active regions having two opposite ends and a center region; wordlines that are buried in and cross the active regions and extend in a second direction, which is different from the first direction, wherein a wordline that crosses an active region crosses between one of the two opposite ends and the center region of the active region; first contact plugs on the two opposite ends of the active regions, each contact plug overlapping a border between the active region and the device isolation layer; and second contact plugs formed on the first contact plugs. | 09-15-2011 |
20110284939 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction. | 11-24-2011 |
20110303974 | INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed. | 12-15-2011 |
20120025300 | Semiconductor Devices Including Vertical Channel Transistors And Methods Of Manufacturing The Same - A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches. | 02-02-2012 |
20120094454 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR - A method of fabricating a semiconductor device including a vertical channel transistor. The method may include: forming a plurality of first device isolation layers in a substrate as a pattern of lines having a first depth from an upper surface of a substrate, to define a plurality of active regions, forming a plurality of trenches having a second depth smaller than the first depth, etching portions of the substrate that are under some of the plurality of trenches that are selected at a predetermined interval, to form a plurality of device isolation trenches having a third depth that is greater than the second depth, forming second device isolation layers that include an insulating material, in lower portions of the plurality of device isolation trenches, and forming buried bit lines in lower portions of the plurality of trenches and the plurality of device isolation trenches. | 04-19-2012 |
20120094455 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other. | 04-19-2012 |
20120119286 | SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME - A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect. | 05-17-2012 |
20120299090 | Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods - A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed. | 11-29-2012 |
20130037882 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench. | 02-14-2013 |
20130113029 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between | 05-09-2013 |
20130115745 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES - Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer. | 05-09-2013 |
20130288472 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING BURIED CHANNEL ARRAY - A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers. | 10-31-2013 |
20140061736 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces. | 03-06-2014 |
20140154882 | METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape. | 06-05-2014 |
20140252440 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUG - Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug. | 09-11-2014 |
20140291804 | SEMICONDUCTOR DEVICES HAVING BALANCING CAPACITOR AND METHODS OF FORMING THE SAME - A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block. | 10-02-2014 |
20140374809 | PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS - An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed. | 12-25-2014 |