Patent application number | Description | Published |
20090027972 | WORDLINE DRIVER FOR A NON-VOLATILE MEMORY DEVICE, A NON-VOLATILE MEMORY DEVICE AND METHOD - A wordline driver, for a non-volatile memory device, comprises a wordline driver output, a first power source, adapted to provide an erase level voltage for erasing portions of the non-volatile memory device, a second power source, adapted to provide read and program level voltages for reading and programming portions of the non-volatile memory device and first switching means, including an isolation transistor, adapted to connect the wordline driver output to a one of the first and second power sources dependent upon an operating mode of the wordline driver. The wordline driver further comprises a programmable switch controller for providing a variable control signal to a control electrode of the isolation transistor. The programmable switch controller is arranged to set the variable control signal to a value dependent upon the operating parameters of the non-volatile memory device and such that the endurance of the isolation transistor is maximised. | 01-29-2009 |
20090097324 | NON-VOLATILE MEMORY DEVICE AND A PROGRAMMABLE VOLTAGE REFERENCE FOR A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a voltage reference generator comprising a programmable voltage reference for generating a voltage signal having a programmable voltage level. In an embodiment, the programmable voltage reference provides the voltage signals for a wordline driver and/or a bitline current generator of the non-volatile memory device. The programmable voltage reference may comprise a Digital-to-Analog converter coupled between first and second supply voltages. A programmable current reference is also disclosed. | 04-16-2009 |
20100164569 | CIRCUIT ARRANGEMENT FOR FILTERING UNWANTED SIGNALS FROM A CLOCK SIGNAL, PROCESSING SYSTEM AND METHOD OF FILTERING UNWANTED SIGNALS FROM A CLOCK SIGNAL - A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement. | 07-01-2010 |
20100253422 | SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter. | 10-07-2010 |
20100277205 | SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which an electronic circuit is provided. One or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an amount of a current flowing between the substrate and at least one of the at least one pad. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter. | 11-04-2010 |
20110297935 | SEMICONDUCTOR DEVICE WITH APPRAISAL CIRCUITRY - A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value. | 12-08-2011 |
20120134060 | ELECTRONIC DEVICE WITH PROTECTION CIRCUIT - An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input. | 05-31-2012 |
20140035638 | SYSTEM AND METHOD FOR CLOCK SIGNAL GENERATION - A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal. | 02-06-2014 |
20140169495 | SIGNALLING CIRCUIT, PROCESSING DEVICE AND SAFETY CRITICAL SYSTEM - A signalling circuit for a signal channel of a communication network comprises a communication network terminal connectable to the signal channel and to a voltage supply; an input terminal connectable to receive a transmit signal; a driver device comprising a first driver terminal connected to the communication network terminal, a second driver terminal connected to ground, and a driver control terminal connected to the input terminal; wherein the driver device is arranged to connect the communication network terminal to ground in response to a transition from a low to a high voltage driver control signal state of a driver control signal received at the driver control terminal. And the signalling circuit comprises a feedback circuit connected to the first driver terminal and the driver control terminal and comprising a capacitive device; and a pull-down device arranged to connect the driver control terminal to ground after a predefined delay after a transition of the transmit signal from a low to a high voltage transmit signal state. | 06-19-2014 |
20150061780 | OSCILLATOR CIRCUIT, A SEMICONDUCTOR DEVICE AND AN APPARATUS - An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase. The second comparator comprises a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output from comparing the second capacitor voltage to the reference voltage and in its zeroing phase in the first half-phase. | 03-05-2015 |