Patent application number | Description | Published |
20090155965 | METHOD OF FABRICATING A NON-FLOATING BODY DEVICE WITH ENHANCED PERFORMANCE - Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region. | 06-18-2009 |
20100176424 | Doping of Semiconductor Fin Devices - A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface. | 07-15-2010 |
20100177289 | Immersion Fluid for Immersion Lithography, and Method of Performing Immersion Lithography - An immersion lithographic system | 07-15-2010 |
20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same - A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described. | 04-05-2012 |
Patent application number | Description | Published |
20150085260 | COLOR WHEEL MODULE AND PROJECTION APPARATUS - A color wheel module and a projection apparatus are provided, wherein the color wheel module includes a color wheel, a cover and a flow detour duct. The cover shades the color wheel. The flow detour duct is communicated with the cover and has an airflow inlet and an airflow outlet. The rotating color wheel is configured to drive airflow into the flow detour duct from the airflow inlet, and cause the airflow through the color wheel and then discharged from the airflow outlet. | 03-26-2015 |
20150092164 | OPTICAL ENGINE MODULE - An optical engine module includes a first casing with a first enclosed space, a light source at the first casing, a phosphor wheel in the first casing, a cooling fan and a heat-dissipating module. The light source emits a light beam passing through the phosphor wheel. The cooling fan is in the first enclosed space and has an airflow outlet. The heat-dissipating module includes two heat-dissipating parts and a heat-guiding part, wherein the first and second heat-dissipating parts are respectively in and outside the first enclosed space, the heat-guiding part is connected between the first and second heat-dissipating parts and the phosphor wheel is between the airflow outlet and the first heat-dissipating part. The airflow outlet and the phosphor wheel, and the phosphor wheel and the first heat-dissipating part, are at least partially overlapped with each other along the airflow exiting direction of the cooling fan. | 04-02-2015 |
20150131061 | LIGHT SOURCE MODULE AND PROJECTION APPARATUS - A light source module and a projection apparatus including the light source module, an optical engine module, and a projection lens are provided. The light source module includes a lamp holder, a casing, a light source, and a heat dissipation fan. The lamp holder has a cover having a first inlet and a first outlet. The casing is connected to the lamp holder and has a second inlet and at least one second outlet. The light source is fixed to the lamp holder fixed to a housing of the projection apparatus. The heat dissipation fan generates a heat dissipation airflow through an outflow side. A first part of the heat dissipation airflow enters the cover through the first inlet, and leaves the cover through the first outlet. A second part of the heat dissipation airflow enters the casing through the second inlet, and leaves the casing through the second outlet. | 05-14-2015 |
Patent application number | Description | Published |
20080217047 | CIRCUIT BOARD SURFACE STRUCTURE - A circuit board surface structure includes a circuit board having at least one surface provided with a plurality of electrically connecting pads, an insulating protective layer characterized by photosensitivity and solder resisting and formed on the circuit board, and a plurality of openings formed in the insulating protective layer to expose the electrical connecting pads on the circuit board and tapered upward; and a conductive element formed in the opening, so as to increase the contact area and reinforce bonding between the electrically connecting pads and the conductive element. | 09-11-2008 |
20080272501 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 11-06-2008 |
20090050359 | Circuit board having electrically connecting structure and fabrication method thereof - A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection. The conductive posts and electrically connecting pads are absent from the insulating protective layer beneath the standalone metal pads, such that circuits can be formed under the insulating protective layer. | 02-26-2009 |
20090134515 | SEMICONDUCTOR PACKAGE SUBSTRATE - A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads. | 05-28-2009 |
20110031617 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 02-10-2011 |
20110056738 | PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A package substrate and a manufacturing method thereof are provided, including: forming a solder mask on a package substrate body having a plurality of conductive pads; forming a plurality of first-step openings in the solder mask by exposure and development; forming a plurality of second-step openings in the solder mask by a laser-based or plasma-based drilling process; and removing a solder mask foot from the bottom of each of the first-step openings so as to expose large surface areas of the conductive pads. Hence, the contact area between a conductive element and a corresponding one of the conductive pads is large enough to enhance bonding and electrical connection therebetween. | 03-10-2011 |
Patent application number | Description | Published |
20120167966 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - A solar cell includes a semiconductor base, a first doped semiconductor layer, an insulating layer, a second doped semiconductor layer and a first electrode layer. The semiconductor base has a first doped type. The first doped semiconductor layer, disposed on the semiconductor base, has a doped contact region. The insulating layer is disposed on the first doped semiconductor layer, exposing the doped contact region. The second doped semiconductor layer is disposed on the insulating layer and the doped contact region. The first doped semiconductor layer, the doped contact region and the second doped semiconductor layer have a second doped type, and a dopant concentration of the second doped semiconductor layer is between that of the first doped semiconductor layer and that of the doped contact region. The first electrode layer is disposed corresponding to the doped contact region. | 07-05-2012 |
20130167919 | SOLAR CELL HAVING BURIED ELECTRODE - Disclosed herein is a solar cell, which includes a first electrode, a buried electrode, a photoelectric conversion layer and a second electrode. The buried electrode is disposed on the first electrode. The photoelectric conversion layer is disposed over the first electrode and the buried electrode. The buried electrode is embedded in the photoelectric conversion layer. The second electrode is arranged in a way such that the photoelectric conversion layer is positioned between the first electrode and the second electrode. | 07-04-2013 |
20130312820 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a semiconductor substrate and a first antireflective layer. The semiconductor substrate has a first-type semiconductor surface and a second-type semiconductor surface opposite to each other. The first antireflective layer includes a plurality of refraction convexes and a coverage layer. The refraction convexes are formed on the second-type semiconductor surface. Each refraction convex includes a first refraction part and a second refraction part. The first refraction parts are conformally coated with the respective second refraction parts, and the first refraction part is configured to have a refractive index greater than the refractive index of the second refraction part. The coverage layer is formed to cover the second-type semiconductor surface and the refraction convexes, and the coverage layer is configured to have a refractive index smaller than the refractive index of the second refraction part. A solar cell manufacturing method is also provided. | 11-28-2013 |
20140007918 | PHOTOVOLTAIC DEVICE - A photovoltaic device provided in the present disclosure includes a superstrate, a lower substrate, a plurality of photovoltaic cells and a package structure. The superstrate is light-transmissive, and arranged in parallel with the substrate. The photovoltaic cells are disposed side-by-side at intervals with each other between the superstrate and the substrate, and a gap zone is defined by two facing lateral surfaces of every two of the neighboring photovoltaic cells. The package structure is sandwiched between the superstrate and the substrate, and encapsulates the photovoltaic cells between the superstrate and the substrate in which a reflection portion is provided in the package structure, and located in the gap zone for reflecting lights from the superstrate back to the photovoltaic cells. | 01-09-2014 |
20140048129 | SOLAR CELL AND FABRICATING METHOD THEREOF - A solar cell includes a substrate. The substrate has a light-receiving surface and a back surface opposite to the light-receiving surface. The substrate includes plural trenches formed on the back surface. The solar cell includes plural n-type diffusion areas and plural p-type diffusion areas alternately disposed on the back surface and the surface of the trenches. The possibility of recombination of the electron-hole pair while moving can be reduced because of the trenches, which are formed in the substrate. | 02-20-2014 |
20140230879 | PHOTOVOLTAIC MODULE - A photovoltaic module includes at least two photovoltaic cells and a ribbon. Each of the photovoltaic cells includes a photovoltaic device, a surface electrode, and a back electrode. The photovoltaic device has a light-receiving surface and a back surface opposite the light-receiving surface. The surface electrode is disposed on the light-receiving surface of the photovoltaic device. The surface electrode includes at least one bus electrode and a plurality of finger electrodes. The bus electrode includes at least two line electrodes disposed on the light-receiving surface of the photovoltaic device. The finger electrodes are disposed on the light-receiving surface of the photovoltaic device and extend in a direction different from the lengthwise direction of the bus electrode. The back electrode is disposed on the back surface of the photovoltaic device. The ribbon electrically connects to the photovoltaic cells. | 08-21-2014 |
20140238475 | SOLAR CELL AND FABRICATION METHOD THEREOF - A solar cell includes a base having a first surface and a second surface opposite to the first surface, a lightly-doped region disposed on the first surface of the base, a semiconductor layer disposed on the lightly-doped region, a first electrode disposed on the first surface of the base, and a second electrode disposed on the second surface of the base. The lightly-doped region has a doping type opposite to the doping type of the base. The bottom of the first electrode is substantially aligned with the interface between the first surface of the base and the lightly-doped region. | 08-28-2014 |
Patent application number | Description | Published |
20120091367 | UV Exposure Method for Reducing Residue in De-Taping Process - A method of forming an integrated circuit includes providing a wafer, and a tape adhered to the wafer, wherein the tape has a main surface perpendicular to a first direction. The tape is exposed to a light to cause the tape to lose adhesion. In the step of exposing the tape, the wafer and the tape are rotated, and/or the light is tilt projected onto the tape, wherein a main projecting direction of the light and the first direction form a tilt angle greater than zero degrees and less than 90 degrees. | 04-19-2012 |
20130241057 | Methods and Apparatus for Direct Connections to Through Vias - Methods and apparatus for direct connection to a through via. An apparatus includes a substrate having a front side surface and a back side surface; conductive through vias formed in the substrate and having through via protrusions extending from the back side surface; solder connectors on another device and coupling the another device to the substrate, wherein the solder connectors correspond to the through via protrusions and enclose the through via protrusions to form solder joints; and connectors on the front side surface of the substrate for forming additional electrical connections. Methods include providing a substrate with through vias; thinning the substrate; etching the substrate to create through via protrusions; aligning another device with solder connectors on a surface corresponding to the through via protrusions; placing the solder connectors in contact with the protrusions; and performing a thermal reflow to form solder joints around the through via protrusions. | 09-19-2013 |
20150024575 | Wafer Alignment Methods in Die Sawing Process - A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface of the wafer. The molding compound covers a center region of the wafer, and leaves an edge ring of the wafer not covered. An opening is formed to extend from the front surface of the wafer into the wafer, wherein the opening is in the edge ring of the wafer. A backside grinding is performed on the wafer until the opening is revealed through a back surface of the wafer. The method further includes determining a position of a scribe line of the wafer using the opening as an alignment mark, and sawing the wafer from a backside of the wafer by sawing through the scribe line. | 01-22-2015 |
20150155249 | Solder Joint Structure for Ball Grid Array in Wafer Level Package - A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed. | 06-04-2015 |