Patent application number | Description | Published |
20120098133 | STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES - The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas. | 04-26-2012 |
20130082329 | MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS - Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position. | 04-04-2013 |
20130082333 | MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS - Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position. | 04-04-2013 |
20140363969 | DOUBLE SELF ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 12-11-2014 |
20140367826 | MAKING AN EFUSE - A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask. | 12-18-2014 |