Patent application number | Description | Published |
20120267799 | PACKAGE STRUCTURES - A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die. | 10-25-2012 |
20130187266 | INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND METHOD OF FORMING THE SAME - An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections. | 07-25-2013 |
20130207258 | POST-PASSIVATION INTERCONNECT STRUCTURE AMD METHOD OF FORMING SAME - A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure. | 08-15-2013 |
20130270698 | STRAIN REDUCED STRUCTURE FOR IC PACKAGING - A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region. | 10-17-2013 |
20130270710 | GUARD RING DESIGN STRUCTURE FOR SEMICONDUCTOR DEVICES - A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells. | 10-17-2013 |
20140131877 | STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES - A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies. | 05-15-2014 |
20140264922 | SEMICONDUCTOR STRUCTURE - One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile. | 09-18-2014 |
20140312454 | Structure Designs and Methods for Integrated Circuit Alignment - Devices and methods for pattern alignment are disclosed. The device includes an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region, and a plurality of die alignment marks disposed within the seal ring region that are alternately disposed adjacent the scribe line region and the assembly isolation region. | 10-23-2014 |
20150014846 | Self-alignment Structure for Wafer Level Chip Scale Package - A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure. | 01-15-2015 |
20150021759 | MECHANISMS FOR FORMING PACKAGE STRUCTURE - Embodiments of mechanisms for forming a package structure are provided. A method for forming a package structure includes providing a semiconductor die and forming a first bump structure and a second bump structure over the semiconductor die. The second bump structure is thinner and wider than the first bump structure. | 01-22-2015 |
20150064845 | METHOD OF FORMING AN INTEGRATED CIRCUIT PACKAGE - A method of fabricating an integrated circuit package assembly comprises forming solder bumps over a first surface of a first integrated circuit package. The method also comprises forming at least one first support structure over the first surface of the first integrated circuit package or over a second surface of a second integrated circuit package. The method further comprises mounting the first integrated circuit package over a second integrated circuit package. The first integrated circuit package is mounted over the second integrated circuit package with the first surface facing the second surface, and the at least one first support structure is electrically isolated. | 03-05-2015 |
20150076689 | Hollow Metal Pillar Packaging Scheme - An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected. | 03-19-2015 |